实验六、流水灯设计 Verilog FPGA

一、流水灯设计实验程序： module led(clk,clr,out); input

input output reg reg reg

[6:0] [6:0] [2:0]

clk; clr; out;

out; count;

flag;//达到3s时的标志位 count1; or negedge

clr) //clk 为2HZ

reg [2:0]

always @(posedge clk if(!clr)

count else

<= 3'b00;

if(count==4) begin count

end

flag

<= count <= 1'b1;

+ 1'b1;

else if(count<4) begin count

flag end

<= count <= 1'b0;

+ 1'b1;

else begin count

flag end

<= 3'b000; <= 1'b0;

always @(posedge flag

if(!clr) count1 else

or negedge clr) //发光二极管移位

<= 3'b000;

if(count1<=5) count1 <= count1 else

count1

<= 3'b000;

+ 1'b1;

always @(clr

if(!clr)

or count1) //点亮二级管

out = 7'b0000000;

else case(count1) 3'b000:out 3'b001:out

3'b010:out 3'b011:out 3'b100:out 3'b101:out 3'b110:out

= = = = = = = =

7'b0000001; 7'b0000010; 7'b0000100; 7'b0001000; 7'b0010000; 7'b0100000; 7'b1000000; 7'b0000000;

default:out endcase

endmodule

二、流水灯设计测试程序： `timescale 1us/100ns module led_test;

reg reg wire

led led1(.clk(clk_test), .clr(clr_test), .out(out_test)); initial

begin #0 end

~clk_test;

#200 #10

clk_test = clr_test = clr_test = clr_test =

1'b0; 1'b1; 1'b0; 1'b1;

[6:0]

clk_test; clr_test; out_test;

always #5 clk_test =

endmodule