C87C251SB16资料

来源：华佗小知识

PRELIMINARY

8XC251SA/SB/SP/SQHIGH-PERFORMANCECHMOS MICROCONTROLLER

Commercial/ExpresssReal-time and Programmed Wait State Bus OperationsBinary-code Compatible with MCS®51sPin Compatible with 44-pin PLCC and 40-pin PDIP MCS51 SocketssRegister-based MCS®251 Architecture—40-byte Register File—Registers Accessible as Bytes, Words, or Double WordssEnriched MCS 51 Instruction Set

—16-bit and 32-bit Arithmetic and Logic Instructions—Compare and Conditional Jump Instructions—Expanded Set of Move InstructionssLinear Addressing

s256-Kbyte Expanded External Code/Data Memory SpacesROM/OTPROM/EPROM Options:

16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or without ROM/OTPROM/EPROMs16-bit Internal Code Fetchs-Kbyte Extended Stack SpacesOn-chip Data RAM Options:

1-Kbyte (SA/SB) or 512-Byte (SP/SQ) s8-bit, 2-clock External Code Fetch in Page ModesFast MCS 251 Instruction Pipeline

sUser-selectable Configurations:

—External Wait States (0-3 wait states)—Address Range & Memory Mapping—Page Mode

s32 Programmable I/O LinessSeven Maskable Interrupt Sources with Four Programmable Priority LevelssThree Flexible 16-bit Timer/counterssHardware Watchdog TimersProgrammable Counter Array—High-speed Output—Compare/Capture Operation—Pulse Width Modulator—Watchdog Timer

sProgrammable Serial I/O Port —Framing Error Detection—Automatic Address RecognitionsHigh-performance CHMOS TechnologysStatic Standby to 16-MHz OperationsComplete System Development Support

—Compatible with Existing Tools—New MCS 251 Tools Available:

Compiler, Assembler, Debugger, ICEsPackage Options (PDIP, PLCC, andCeramic DIP)

A member of the Intel family of 8-bit MCS251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-codecompatible with MCS51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS51microcontrollers. MCS251 microcontrollers feature an enriched instruction set, linear addressing, andefficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and isavailable with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.A variety of features can be selected by new user-programmable configurations.

Information in this document is provided in connection with Intel products. No license, express or implied, byestoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided inIntel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Inteldisclaims any express or implied warranty, relating to sale and/or use of Intel products including liability orwarranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyrightor other intellectual property right. Intel products are not intended for use in medical, life saving, or lifesustaining applications.

Intel retains the right to make changes to specifications and product descriptions at any time, without notice.*Third-party brands and names are the property of their respective owners.

Copies of documents which have an ordering number and are referenced in this document, or other Intelliterature, may be obtained from:Intel CorporationP.O. Box 71

Mt. Prospect IL 60056-7or call 1-800-548-4725

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

System Bus and I/O PortsP0.7:0P2.7:0Code󰀀OTPROM/ROM󰀀8 Kbytes󰀀or󰀀16 KbytesI/O Ports and 󰀀Peripheral SignalsP1.7:0P3.7:0Port 0󰀀DriversPort 2󰀀DriversData RAM󰀀512 Bytes󰀀or󰀀1024 BytesPort 1󰀀DriversPort 3󰀀DriversMemory Data (16)Watchdog󰀀TimerPeripheral󰀀InterfaceTimer/󰀀CountersMemory Address (16)Bus InterfaceCode Bus (16)Code Address (24)Instruction SequencerData Address (24)Interrupt󰀀HandlerIB Bus (8)PCASRC2 (8)Data Bus (8)SRC1 (8)ALURegister󰀀FileData󰀀Memory󰀀InterfaceClock󰀀&󰀀ResetSerial I/OPeripheralsDST (16)MCS® 251 Microcontroller CoreClock & Reset8XC251SA/SB/SP/SQ MicrocontrollerA4214-01Figure 1. 8XC251SA/SB/SP/SQ Block Diagram PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

1.0NOMENCLATURE

XTeXXPack8XoPrXoPrXXXXXoPrXXvicDeFigure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature

Table 1. Description of Product Nomenclature

Parameter

Temperature and Burn-in Options

Optionsno mark

Packaging Options

NPC

Program Memory Options

037

Process InformationProduct Family

Device Memory Options

C251SASBSPSQ

Device Speed

Description

Commercial operating temperature range (0°C to 70°C) with Intel standard burn-in.

Express operating temperature range (-40°C to 85°C) with Intel standard burn-in.

44-pin Plastic Leaded Chip Carrier (PLCC)40-pin Plastic Dual In-line Package (PDIP)

40-pin Ceramic Dual In-line Package (Ceramic DIP)Without ROM/OTPROM/EPROMROM

User programmable OTPROM/EPROMCHMOS

8-bit control architecture

1-Kbyte RAM/8-Kbyte ROM/OTPROM/EPROM

1-Kbyte RAM/16-Kbyte ROM/OTPROM/EPROM or without ROM/OTPROM/EPROM

512-byte RAM/8-Kbyte ROM/OTPROM/EPROM

512-byte RAM/16-Kbyte ROM/OTPROM/EPROM or without ROM/OTPROM/EPROMExternal clock frequency

mpgramsscedustioonOpptiin On-uring Bagndedpee SatuermFact fo In-m areemrmatiilyory OonsonptinsA2815-014

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 2 lists the proliferation options. See Figure 2 for the 8XC251SA/SB/SP/SQ family nomenclature.

Table 2. Proliferation Options

8XC251SA/SB/SP/SQ(0 – 16 MHz; 5 V ±10%)

80C251SB16CPU-only80C251SQ16CPU-only83C251SA16ROM83C251SB16ROM83C251SP16ROM83C251SQ16ROM

87C251SA16OTPROM/EPROM87C251SB16OTPROM/EPROM87C251SP16OTPROM/EPROM87C251SQ16

OTPROM/EPROM

Table 3 lists the 8XC251SA/SB/SP/SQ packages.

Table 3. Package Information

Pkg.DefinitionTemperatureN44 ld. PLCC0°C to +70°CP40 ld. Plastic DIP0°C to +70°CC40 ld. Ceramic DIP0°C to +70°CTN44 ld. PLCC-40°C to +85°CTP

40 ld. Plastic DIP

-40°C to +85°C

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

2.0PINOUT

P1.5 / CEX2󰀀P1.6 / CEX3 / WAIT#󰀀P1.7 / CEX4 / A17 / WCLK󰀀RST󰀀P3.0 / RXD󰀀VCC2P3.1 / TXD󰀀P3.2 / INT0#󰀀P3.3 / INT1#󰀀P3.4 / T0󰀀P3.5 / T17󰀀8󰀀9󰀀10󰀀11󰀀12󰀀13󰀀14󰀀15󰀀16󰀀176543214443424140P1.4 / CEX1P1.3 / CEX0P1.2 / ECIP1.1 / T2EXP1.0 / T2VSS1VCCAD0 / P0.0AD1 / P0.1 AD2 / P0.2 AD3 / P0.38XC251SA󰀀8XC251SB󰀀8XC251SP󰀀8XC251SQView of component as󰀀mounted on PC board181920212223242526272839󰀀38󰀀37󰀀36󰀀35󰀀34󰀀33󰀀32󰀀31󰀀30󰀀29AD4 / P0.4󰀀AD5 / P0.5󰀀AD6 / P0.6󰀀AD7 / P0.7󰀀EA# / VPPVSS2ALE / PROG#󰀀PSEN#󰀀A15 / P2.7󰀀A14 / P2.6󰀀A13 / P2.5P3.6 / WR# P3.7 / RD# / A16XTAL2XTAL1VSSVSS2A8 / P2.0A9 / P2.1A10 / P2.2A11 / P2.3A12 / P2.4A4205-02Figure 3. 8XC251SA/SB/SP/SQ 44-pin PLCC Package

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

P1.0 / T2󰀀P1.1 / T2EX󰀀P1.2 / ECI󰀀P1.3 / CEX0󰀀P1.4 / CEX1󰀀P1.5 / CEX2󰀀P1.6 / CEX3 / WAIT#󰀀P1.7 / CEX4 / A17 / WCLK󰀀RST󰀀P3.0 / RXDP3.1 / TXD󰀀P3.2 / INT0#󰀀P3.3 / INT1#󰀀P3.4 / T0󰀀P3.5 / T1󰀀P3.6 / WR#󰀀P3.7 / RD# / A16󰀀XTAL2󰀀XTAL1󰀀VSS1󰀀2󰀀3󰀀4󰀀5󰀀6󰀀7󰀀8󰀀9󰀀10󰀀11󰀀12󰀀13󰀀14󰀀15󰀀16󰀀17󰀀18󰀀19󰀀2040󰀀39󰀀38󰀀37󰀀36󰀀35󰀀34󰀀33󰀀32󰀀31󰀀30󰀀29󰀀28󰀀VCC󰀀AD0 / P0.0󰀀AD1 / P0.1󰀀AD2 / P0.2󰀀AD3 / P0.3󰀀AD4 / P0.4󰀀AD5 / P0.5󰀀AD6 / P0.6󰀀AD7 / P0.7󰀀EA# / VPP󰀀ALE / PROG#󰀀PSEN#󰀀A15 / P2.7󰀀A14 / P2.6󰀀A13 / P2.5󰀀A12 / P2.4󰀀A11 / P2.3󰀀A10 / P2.2󰀀A9 / P2.1󰀀A8 / P2.0A4206-038XC251SA󰀀8XC251SB󰀀8XC251SP󰀀8XC251SQView of󰀀component󰀀as mounted󰀀on PC board27󰀀26󰀀25󰀀24󰀀23󰀀22󰀀21Figure 4. 8XC251SA/SB/SP/SQ 40-pin PDIP and Ceramic DIP Packages

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Table 4. 8XC251SA/SB/SP/SQ Pin Assignment

PLCCDIP

Name

1VSS121P1.0/T232P1.1/T2EX43P1.2/ECI54P1.3/CEX065P1.4/CEX176P1.5/CEX287P1.6/CEX3/WAIT#98P1.7/CEX4/A17/WCLK109RST1110P3.0/RXD12VCC21311P3.1/TXD1412P3.2/INT0#1513P3.3/INT1#1614P3.4/T01715P3.5/T11816P3.6/WR#1917P3.7/RD#/A162018XTAL22119XTAL122

20VSS

PLCCDIP

Name

23VSS22421A8/P2.02522A9/P2.12623A10/P2.22724A11/P2.32825 A12/P2.42926A13/P2.53027A14/P2.63128A15/P2.73229PSEN#3330ALE/PROG#34VSS23531EA#/VPP3632AD7/P0.73733AD6/P0.63834AD5/P0.53935AD4/P0.44036AD3/P0.34137AD2/P0.24238AD1/P0.14339AD0/P0.044

40VCC

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Table 5. 8XC251SA/SB/SP/SQ PLCC/DIP Pin Assignments Arranged by Functional Category

Address & DataName

PLCCDIPAD0/P0.04339AD1/P0.14238AD2/P0.24137AD3/P0.34036AD4/P0.43935AD5/P0.53834AD6/P0.63733AD7/P0.73632A8/P2.02421A9/P2.12522A10/P2.22623A11/P2.32724A12/P2.42825A13/P2.52926A14/P2.63027A15/P2.73128P3.7/RD#/A161917P1.7/CEX4/A17/WCLK

Processor ControlName

PLCCDIPP3.2/INT0#1412P3.3/INT1#1513EA#/VPP3531RST109XTAL12118XTAL2

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Input/OutputName

PLCCDIPP1.0/T221P1.1/T2EX32P1.2/ECI43P1.3/CEX054P1.4/CEX165P1.5/CEX276P1.6/CEX3/WAIT#87P1.7/CEX4/A17/WCLK98P3.0/RXD1110P3.1/TXD1311P3.4/T01614P3.5/T1

Power & GroundName

PLCCDIPVCC4440

VCC212VSS2220VSS11VSS2

23, 34

EA#/VPP 3531Bus Control & StatusName

PLCCDIPP3.6/WR#1816P3.7/RD#/A161917ALE/PROG#3330PSEN#

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

3.0SIGNALS

Table 6. Signal Descriptions

Alternate FunctionP1.7/CEX4/WCLK

Signal NameA17

TypeO

Description

18th Address Bit (A17). Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4, “Device Configuration,” of the 8XC251SA/SB/SP/SQ Embedded Microcontroller User’s Manual). See also RD# and PSEN#. Address Line 16. See RD#.

Address Lines. Upper address lines for the external bus.

Address/Data Lines. Multiplexed lower address lines and data lines for external memory.

Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus.

A16A15:8†AD7:0†ALE

OOI/OO

RD#P2.7:0P0.7:0PROG#

CEX4:0I/O

Programmable Counter Array (PCA) Input/Output Pins. These are P1.6:3input signals for the PCA capture mode and output signals for the PCA P1.7/A17/compare mode and PCA PWM mode. WAIT#External Access. Directs program memory accesses to on-chip or off-VPPchip code memory. For EA# = 0, all program memory accesses are off-chip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if the address is within the range of the on-chip

ROM/OTPROM/EPROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without on-chip

ROM/OTPROM/EPROM, EA# must be strapped to ground.PCA External Clock Input. External clock input to the 16-bit PCA timer.

External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#.

Programming Pulse. The programming pulse is applied to this pin for programming the on-chip OTPROM.

Port 0. This is an 8-bit, open-drain, bidirectional I/O port.Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.

P1.2P3.3:2

EA#I

ECIINT1:0#

PROG#P0.7:0P1.0P1.1P1.2P1.7:3

II/OI/O

ALEAD7:0T2T2EXECICEX3:0CEX4/A17/WAIT#/WCLKA15:8

P2.7:0

†

I/OPort 2. This is an 8-bit, bidirectional I/O port with internal pullups.

The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-patible with 44-pin PLCC and 40-pin DIP MCS51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 6. Signal Descriptions (Continued)

Signal NameP3.0P3.1P3.3:2P3.5:4P3.6P3.7PSEN#

TypeI/O

Description

Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.

Alternate FunctionRXDTXDINT1:0#T1:0WR#RD#/A16—

Program Store Enable. Read signal output. This output is asserted for a memory address range that depends on bits RD0 and RD1 in configuration byte UCONFIG0 (see RD# and Chapter 4, “Device Con-figuration,” in the 8XC251SA/SB/SP/SQ Embedded Microcontroller User’s Manual).

RD#O

Read or 17th Address Bit (A16). Read signal output to external data P3.7/A16memory or 17th external address bit (A16), depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and Chapter 4, “Device Configuration,” in the 8XC251SA/SB/SP/SQ Embedded Microcontroller User’s Manual).

Reset. Reset input to the chip. Holding this pin high for oscillator —periods while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an inter-nal pulldown resistor, which allows the device to be reset by connect-ing a capacitor between this pin and VCC.

Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation.

Receive Serial Data. RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3.

Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count.

P3.0P3.5:4

RSTI

RXDT1:0T2

I/OI I/O

Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal P1.0is the external clock input. For the clock-out mode, it is the timer 2 clock output.

Timer 2 External Input. In timer 2 capture mode, a falling edge ini-tiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. In the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down.

P1.1

T2EXI

TXDVCCVCC2

OPWRPWR

Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 P3.1and transmits serial data in serial I/O modes 1, 2, and 3. Supply Voltage. Connect this pin to the +5V supply voltage.

Secondary Supply Voltage 2. This supply voltage connection is pro-vided to reduce power supply noise. Connection of this pin to the +5V supply voltage is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be uncon-nected without loss of compatibility. (Not available on DIP)

——

†

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 6. Signal Descriptions (Continued)

Signal NameVPPVSSVSS1

TypeIGNDGND

Description

Programming Supply Voltage. The programming supply voltage is applied to this pin for programming the on-chip OTPROM/EPROM. Circuit Ground. Connect this pin to ground.

Alternate FunctionEA#—

Secondary Ground. This ground is provided to reduce ground bounce —and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SA/SB/SP/SQ as a pin-for-pin replacement for the 8XC51BH, VSS1 can be unconnected without loss of compatibility. (Not available on DIP)

Secondary Ground 2. This ground is provided to reduce ground

bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP)

—

VSS2

GND

WAIT#I

Real-time Wait State Input. The real-time WAIT# input is enabled by P1.6/CEX3writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus cycles, the external memory system can signal ‘system ready’ to the microcontroller in real time by controlling the WAIT# input signal on the port 1.6 input.

Wait Clock Output. The real-time WCLK output is driven at port 1.7 (WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H. When enabled, the WCLK output produces a square wave signal with a period of one-half the oscillator frequency.Write. Write signal output to external memory.

Input to the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing.

Output of the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected.

P1.7/CEX4/A17

WCLKO

WR#XTAL1

P3.6—

XTAL2O—

†

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Table 7. Memory Signal Selections (RD1:0)

RD1:00 00 11 0

P1.7/CEX/A17/WCLKA17P1.7/CEX4/WCLKP1.7/CEX4/WCLKP1.7/CEX4/WCLK

P3.7/RD#/A16 PSEN#A16A16P3.7 only

Asserted for all addressesAsserted for all addressesAsserted for all addressesAsserted for ≥ 80:0000H

WR#

Asserted for writes to all memory locationsAsserted for writes to all memory locationsAsserted for writes to all memory locationsAsserted only for writes to MCS 51 microcontroller data memory locations.

Features256-Kbyte external memory

128-Kbyte external memory

-Kbyte external memory. One additional port pin.-Kbyte external memory. Compatible with MCS 51 micro-controllers.

1 1

RD# asserted for addresses≤ 7F:FFFFH

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4.0ADDRESS MAP

Table 8. 8XC251SA/SB/SP/SQ Address Map

Internal Address)FF:FFFFHFF:4000HFF:3FFFHFF:0000HFE:FFFFHFE:0000HFD:FFFFH02:0000H01:FFFFH01:0000H00:FFFFH00:E000H00:DFFFH00:0420H00:041FH00:0080H00:007FH00:0020H 00:001FH00:0000H

Description

External Memory except the top eight bytes (FF:FFF8H–FF:FFFFH) which are reserved for the configuration array.

External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH, 16Kbytes FF:0000H - FF:3FFFH).External Memory

Notes1, 3, 103, 4, 53

Reserved6

External Memory

External memory or with configuration bit EMAP# = 0, addresses in this range access on-chip code memory in region FF: (16 Kbyte devices only).External Memory

On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H - 00:041FH)On-chip RAM

Storage for R0–R7 of Register File

35, 77782, 9

NOTES:

1.18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).

2.The special function registers (SFRs) and the register file have separate internal address spaces.3.Data in this area is accessible by indirect addressing only.

4.Devices reset into internal or external starting locations depending on the state of EA# and configura-tion byte information See EA#. See also UCONFIG1:0 bit definitions in the 8XC251SA/SB/SP/SQ Embedded Microcontroller User’s Manual.

5.The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H–FF:3FFFH to map

into region 00:. In this case, if EA# = 1, a data read to 00:E000H–00:FFFFH is redirected to internal ROM/OTPROM/EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte ROM/OTPROM/EPROM devices.

6.This reserved area returns indeterminate values. 7.Data is accessible by direct and indirect addressing.8.Data is accessible by direct, indirect, and bit addressing.

9.Data is accessible by direct, indirect, and register addressing.

10.Eight addresses at the top of all external memory maps are reserved for current and future device

configuration byte information.

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5.0ELECTRICAL CHARACTERISTICS

NOTICE: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

†

ABSOLUTE MAXIMUM RATINGS

Storage Temperature ................................... -65°C to +150°CVoltage on EA#/VPP Pin to VSS......................... 0 V to +13.0 VVoltage on Any other Pin to VSS..................... -0.5 V to +6.5 VIOL per I/O Pin.................................................................15 mAPower Dissipation.......................................................... 1.5 W

VSS ..................................................................................... 0 V

WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause perma-nent damage. These are stress ratings only. Oper-TA (Ambient Temperature Under Bias):

Commercial.................................................0°C to +70°Cation beyond the “Operating Conditions” is not Express....................................................-40°C to +85°Crecommended and extended exposure beyond the “Operating Conditions” may affect device VCC (Digital Supply Voltage) .............................. 4.5 V to 5.5 V

reliability.OPERATING CONDITIONS†

NOTE

Maximum power dissipation is based on package heat-transfer limitations, not device power consumption.

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5.1D.C. Characteristics

Parameter values apply to all devices unless otherwise indicated.

Table 9. DC Characteristics at VCC = 4.5 – 5.5 V

SymbolVILVIL1VIHVIH1VOL

ParameterInput Low Voltage (except EA#)Input Low Voltage (EA#)

Input High Voltage (except XTAL1, RST)Input High Voltage (XTAL1, RST)Output Low Voltage (Port 1, 2, 3)

Min-0.500.2VCC + 0.90.7VCC

Typical

Max0.2VCC – 0.10.2VCC – 0.3VCC + 0.5VCC + 0.50.30.451.00.30.451.0

VCC – 0.3VCC – 0.7VCC – 1.5

UnitsVVVVV

IOL = 100 µA IOL = 1.6 mA IOL = 3.5 mA(Note 1, Note 2)IOL = 200 µAIOL = 3.2 mAIOL = 7.0 mA(Note 1, Note 2)IOH = -10 µAIOH = -30 µAIOH = -60 µA(Note 3)

Test Conditions

VOL1

Output Low Voltage (Port 0, ALE, PSEN#)

VOH

Output High Voltage (Port 1, 2, 3, ALE, PSEN#)

NOTES:

1.Under steady-state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:10 mAMaximum IOL per 8-bit port:

port 026 mAports 1–315 mAMaximum Total IOL for

all output pins

71 mA

If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.2.

Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic.

Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-tion when the address lines are stabilizing.

Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.

3.4.

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Continued)

SymbolVOH1

ParameterOutput High Voltage (Port 0 in External Address)

Output High Voltage (Port 2 in External Address during Page Mode)

Logical 0 Input Cur-rent (Port 1, 2, 3)Input Leakage Cur-rent (Port 0)

Logical 1-to-0 Transi-tion Current (Port 1, 2, 3)

RST Pulldown Resis-tor

Pin CapacitancePowerdown Current Idle Mode Current Operating Current

10 (Note 4)10(Note 4)12(Note 4)45(Note 4)

201580

MinVCC – 0.3VCC – 0.7VCC – 1.5VCC – 0.3 VCC – 0.7 VCC – 1.5

-50+/-10-650

Typical

Max

UnitsV

Test ConditionsIOH = -200 µAIOH = -3.2 mAIOH = -7.0 mAIOH = -200 µA IOH = -3.2 mAIOH = -7.0 mA VIN = 0.45 V0.45 < VIN < VCCVIN = 2.0 V

VOH2

IILILIITL

µAµAµA

RRSTCIOIPDIDLICC

225kΩpFµAmAmA

FOSC = 16 MHzFOSC = 16 MHzFOSC = 16 MHzTA = 25 °C

NOTES:

1.Under steady-state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:10 mAMaximum IOL per 8-bit port:

port 026 mAports 1–315 mAMaximum Total IOL for

all output pins

71 mA

If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.2.

Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-tion when the address lines are stabilizing.

Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.

3.4.

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

VCCVCCP0RST8XC251SA󰀀8XC251SB󰀀8XC251SP󰀀8XC251SQ(NC)XTAL2XTAL1VSSEA#IPDVCCAll other 8XC251SA/SB/SP/SQ pins are unconnected.A4208-01Figure 5. IPD Test Condition, Powerdown Mode, VCC = 2.0 – 5.5V

70󰀀60󰀀50󰀀ICC (mA)40󰀀30󰀀20󰀀10󰀀0x maAc mtive (modeA)typ e (mdomive ActA)max Idle mode (mA))typ Idle mode (mA91011121314151612345678Frequency at XTAL (MHz)A4400-01 Figure 6. ICC vs. Frequency (Mhz)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

5.2

Definition of AC Symbols

Table 10. AC Timing Symbol Definitions

Signals

ADLQRW

AddressData InALEData OutRD#/PSEN#WR#

HLVXZ

Conditions

HighLowValid

No Longer ValidFloating

5.3A.C. Characteristics

Test Conditions: Capacitive load on all pins = 50 pF. Table 11 lists AC timing parameters for the8XC251SA/SB/SP/SQ with no wait states. Externalwait states can be added by extendingPSEN#/RD#/WR# and/or by extending ALE. In thetable, Notes 3 and 5 mark parameters affected by an

ALE wait state, and Notes 4 and 5 mark parametersaffected by a PSEN#/RD#/WR# wait state. Figures 8–10 show the bus cycles with the timingparameters.

Table 11. AC Characteristics

SymbolFOSCTOSC

Parameter

XTAL1 Frequency1/FOSC

@ 12 MHz@ 16 MHz

73.352.558.337.51515

@ Max Fosc (1)MinN/AN/A

MaxN/AN/A

Fosc VariableMin083.362.5(1+2M) TOSC – 10(1+2M) TOSC – 25

Max16

UnitsMHzns

TLHLL

ALE Pulse Width

@ 12 MHz@ 16 MHzAddress Valid to ALE Low

@ 12 MHz@ 16 MHzAddress Hold after ALE Low

@ 12 MHz@ 16 MHz

ns(3)ns(3)ns

TAVLL

TLLAX

NOTES:

1.16 MHz.

2.Specifications for PSEN# are identical to those for RD#.3.In the formula, M=Number of wait states (0 or 1) for ALE.

4.In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.5.“Typical” specifications are untested and not guaranteed.

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 11. AC Characteristics(Continued)

SymbolTRLRH (2)

Parameter

RD# or PSEN# Pulse Width

@ 12 MHz@ 16 MHzWR# Pulse Width

@ 12 MHz@ 16 MHz

ALE Low to RD# or PSEN# Low

@ 12 MHz@ 16 MHzALE High to Address Hold

@ 12 MHz@ 16 MHz

RD#/PSEN# Low to valid Data/Instruction In

@ 12 MHz@ 16 MHz

0Typ.=0 2(5)Typ.=218510Typ.=25(5)

156.6115

1010156.6115171.6130

@ Max Fosc (1)Min146.6105146.610558.337.583.362.5

106.665

0Typ. = 0 (5)Typ.=25Typ.=25(5)

Max

Fosc VariableMin2(1+N)TOSC – 202(1+N)TOSC – 20

Max

Unitsns(4)ns(4)ns

TOSC – 25(1+2M)TOSC

ns(3)ns(4)nsnsns

TWLWH

TLLRL (2)

TLHAX

TRLDV (2)

2(1+N)Tosc – 60

TRHDX (2)Data/Instruction Hold Time. Occurs after

RD#/PSEN# are exerted to VOH TRLAZ (2)TRHDZ1

RD#/PSEN# Low to Address FloatInstruction Float after RD#/PSEN# High

commercial @ 12 MHz and 16 MHzexpress @ 12 MHz and 16 MHz

1810

TRHDZ2

Data Float after RD#/PSEN# High

@ 12 MHz@ 16 MHz

RD#/PSEN# High to ALE High (Instruction)

@ 12 MHz@ 16 MHzRD#/PSEN# High to ALE High (Data)

@ 12 MHz@ 16 MHzWR# High to ALE High

@ 12 MHz@ 16 MHz

2Tosc – 10

TRHLH1

2Tosc - 10

2Tosc + 5

TRHLH2

TWHLH

NOTES:

1.16 MHz.

2.Specifications for PSEN# are identical to those for RD#.3.In the formula, M=Number of wait states (0 or 1) for ALE.

4.In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.5.“Typical” specifications are untested and not guaranteed.

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 11. AC Characteristics(Continued)

SymbolTAVDV1

Parameter

Address (P0) Valid to Valid Data/Instruction In

@ 12 MHz@ 16 MHzAddress (P2) Valid to Valid Data/Instruction In

@ 12 MHz@ 16 MHzAddress (P0) Valid to Valid Instruction In

@ 12 MHz@ 16 MHzAddress Valid to RD#/PSEN# Low

@ 12 MHz@ 16 MHzAddress (P0) Valid to WR# Low

@ 12 MHz@ 16 MHzAddress (P2) Valid to WR# Low

@ 12 MHz@ 16 MHzData Hold after WR# High

@ 12 MHz@ 16 MHzData Valid to WR# High

@ 12 MHz@ 16 MHzWR# High to Address Hold

@ 12 MHz@ 16 MHz

121.680126.685146.610563.342.5138.697156.6115

@ Max Fosc (1)Min

Max243.2160268.2185116.675

2(1+M)TOSC – 452(1+M)TOSC – 402(1+M)TOSC – 20TOSC – 20

Fosc VariableMin

Max4(1+M/2)TOSC – 904(1+M/2)TOSC – 652TOSC – 50

Unitsns(3)ns(3) ns

TAVDV2

TAVDV3

TAVRL (2)

ns(3)ns(3)ns(3)ns

TAVWL1

TAVWL2

TWHQX

TQVWH

2(1+N)TOSC – 282TOSC – 10

ns(4)ns

TWHAX

NOTES:

1.16 MHz.

2.Specifications for PSEN# are identical to those for RD#.3.In the formula, M=Number of wait states (0 or 1) for ALE.

4.In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#.5.“Typical” specifications are untested and not guaranteed.

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

5.3.1

EXTERNAL BUS CYCLES, NONPAGE MODE

TOSCXTAL1ALETLHLL†TLLRL†TRLRH†TRHLH1RD#/PSEN#TRLDV†TRLAZTLHAX†TAVLL†P0TLLAXTRHDZ1TRHDXD7:0Instruction InA7:0TAVRL†TAVDV1†TAVDV2†P2/A16/A17A15:8/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics.A4211-03Figure 7. External Bus Cycle: Code Fetch (Nonpage Mode)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

TOSCXTAL1ALETLHLL†TRLRH†TLLRL†TRHLH2RD#/PSEN#TRLDV†TRLAZTLHAX†TAVLL†P0TRHDZ2TLLAXTRHDXD7:0Data InA7:0TAVRL†TAVDV1†TAVDV2†P2/A16/A17A15:8/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics.A4210-03Figure 8. External Bus Cycle: Data Read (Nonpage Mode)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

TOSCXTAL1ALETLHLL†TWLWH†WR#TLHAX†TAVLL†TLLAXP0A7:0TAVWL1†TAVWL2†A15:8/A16/A17TWHLHTQVWHTWHQXD7:0Data OutTWHAXP2/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics.A4179-01Figure 9. External Bus Cycle: Data Write (Nonpage Mode)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

5.3.2EXTERNAL BUS CYCLES, PAGE MODE

TOSCXTAL1ALETLHLL†TLLRL†RD#/PSEN#TRLDV†TRLAZTLHAX†TAVLL†P2TLLAXD7:0Instruction InTAVDV3A7:0/A16/A17Page Hit††TRHDZ1TRHDXD7:0Instruction In†††A15:8TAVRL†TAVDV1†TAVDV2†P0/A16/A17A7:0/A16/A17Page Miss††† The value of this parameter depends on wait states. See the table of AC characteristics.󰀀†† A page hit (i.e., a code fetch to the same 256-byte \"page\" as the previous code fetch) requires one󰀀 state (2TOSC); a page miss requires two states (4TOSC).󰀀††† During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle. A4213-02Figure 10. External Bus Cycle: Code Fetch (Page Mode)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

TOSCXTAL1ALETLHLL†TLLRL†TRLRH†TRHLH2TRLDV†TRLAZRD#/PSEN#TLHAX†TAVLL†P2TRHDZ2TLLAXTRHDXD7:0Data InA15:8TAVRL†TAVDV1†TAVDV2†P0/A16/A17A7:0/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics. A4212-03Figure 11. External Bus Cycle: Data Read (Page Mode)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

TOSCXTAL1ALETLHLL†TWLWH†WR#TLHAX†TAVLL†TLLAXP2A15:8TAVWL1†TAVWL2†A7:0/A16/A17TWHLHTQVWHTWHQXD7:0Data OutTWHAXP0/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics. A4182-01Figure 12. External Bus Cycle: Data Write (Page Mode)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

5.3.3

DEFINITION OF REAL-TIME WAIT SYMBOLS

Table 12. Real-time Wait Timing Symbol Definitions

Signals

ADCYWR

AddressDataWCLKWAIT#WR#RD#/PSEN#

LXV

Conditions

LowHoldSetup

5.3.4EXTERNAL BUS CYCLES, REAL-TIME WAIT STATES

State 1WCLKALEState 2State 3State 1 (next cycle)TCLYX minTCLYX maxTCLYVRD#/PSEN# stretchedTRLYX maxTRLYX minTRLYVRD#/PSEN#WAIT#P0P2A0-A7D0-D7A8-A15stretchedstretchedA0-A7A8-A15A5000-01Figure 13. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

State 1WCLKState 2State 3State 4TCLYX minALETCLYVWR#TWLYX maxTWLYX minTWLYVWAIT#P0P2A0-A7A8-A15D0-D7stretchedstretchedA5002-01TCLYX maxWR# stretchedFigure 14. External Bus Cycle: Data Write (Nonpage Mode)

State 1WCLKALEState 2State 3State 1 (next cycle)TCLYX minTCLYX maxTCLYVRD#/PSEN# stretchedTRLYX maxTRLYX minTRLYVRD#/PSEN#WAIT#P2P0A8-A15D0-D7A0-A7stretchedstretchedA8-A15A0-A7A5001-01Figure 15. External Bus Cycle: Code Fetch/Data Read (Page Mode)

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

State 1WCLKState 2State 3State 4TCLYX minALETCLYVWR#TWLYX maxTWLYX minTWLYVWAIT#P2P0A8-A15A0-A7D0-D7stretchedstretchedA5003-01TCLYX maxWR# stretchedFigure 16. External Bus Cycle: Data Write (Page Mode)

Table 13. Real-time Wait AC Timing

SymbolTCLYVTCLYXTRLYVTRLYXTWLYVTWLYX

Parameter

Wait Clock Low to Wait Set-upWait Hold after Wait Clock LowPSEN#/RD# Low to Wait Set-upWait Hold after PSEN#/RD# LowWR# Low to Wait Set-upWait Hold after WR# Low

Min0(2W)TOSC + 5

0(2W)TOSC + 5

MaxTOSC – 20(1+2W)TOSC – 20

TOSC – 20(1+2W)TOSC – 20

Unitsnsnsnsnsnsns

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

5.4AC Characteristics — Serial Port, Shift Register Mode

Table 14. Serial Port Timing — Shift Register Mode

Parameter

Serial Port Clock Cycle Time

Output Data Setup to Clock Rising EdgeOutput Data hold after Clock Rising EdgeInput Data Hold after Clock Rising EdgeClock Rising Edge to Input Data Valid

Min12TOSC10TOSC – 1332TOSC – 117

10TOSC – 133

Max

Unitsnsnsnsnsns

SymbolTXLXLTQVSHTXHQXTXHDXTXHDV

TXLXLTXDTXHQXTQVXH0TXHDV123456Set TI†7RXD(Out)TXHDXValidValidTAV†Set RI†ValidValidValidValidRXD(In)ValidValid†TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.A2592-02Figure 17. Serial Port Waveform — Shift Register Mode

5.5External Clock Drive

Table 15. External Clock Drive

Symbol1/TCLCLTCHCXTCLCXTCLCHTCHCL

Parameter

Oscillator Frequency (FOSC)

High TimeLow TimeRise TimeFall Time

2020

1010

Min

Max16

UnitsMHznsnsnsns

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

VCC – 0.50.7 VCC TCLCHTCHCXTCLCX0.45 V0.2 VCC – 0.1 TCHCLTCLCLA4119-01Figure 18. External Clock Drive Waveforms

InputsVCC – 0.50.45 VOutputs0.2 VCC + 0.90.2 VCC – 0.1VIH MINVOL MAXAC inputs during testing are driven at VCC – 0.5V for a logic 1󰀀and 0.45 V for a logic 0. Timing measurements are made at 󰀀a min of VIH for a logic 1 and VOL for a logic 0.A4118-01Figure 19. AC Testing Input, Output Waveforms

VLOAD + 0.1 VVLOADVLOAD – 0.1 VTiming Reference󰀀PointsVOH – 0.1 VVOL + 0.1 VFor timing purposes, a port pin is no longer floating when a 󰀀100 mV change from load voltage occurs and begins to float󰀀when a 100 mV change from the loading VOH/VOL level occurs 󰀀with IOL/IOH = ± 20 mA.A4117-01Figure 20. Float Waveforms

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

6.0THERMAL CHARACTERISTICS

Table 16. Thermal CharacteristicsPackage Type44-pin PLCC40-pin PDIP40-pin Ceramic DIP

θJA46°C/W45°C/W30.5°C/W

θJC16°C/W16°C/W10°C/W

All thermal impedance data is approximate for staticair conditions at 1 watt of power dissipation. Valueschange depending on operating conditions andapplication requirements. The Intel PackagingHandbook (order number 240800) describes Intel’sthermal impedance test methodology.

7.0

NONVOLATILE MEMORY PROGRAMMING AND VERIFICATION CHARACTERISTICS

Definition of Nonvolatile Memory Symbols

Table 17. Nonvolatile Memory Timing Symbol Definitions

7.1

Signals

ADQSGE

AddressData InData OutSupplyPROG#Enable

HLVXZ

Conditions

HighLowValid

No Longer ValidFloating

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

7.2Programming and Verification Timing for Nonvolatile Memory

Programming CycleP1, P3Address (16 Bits)Verification CycleAddressTAVQVP2Data In (8 Bits)TDVGLTAVGLTGHGLTGHDXTGHAXData OutPROG#TGLGHTSHGLEA#/VPP12.75V5VTELQVTEHSHP0Mode (8 Bits)Mode A4128-0112345TGHSLTEHQZFigure 21. Timing for Programming and Verification of Nonvolatile Memory

Table 18. Nonvolatile Memory Programming and Verification Characteristics at

TA = 21 – 27 °C, VCC = 5 V, and VSS = 0 V

Definition

Programming Supply VoltageProgramming Supply CurrentOscillator Frequency

Address Setup to PROG# LowAddress Hold after PROG#Data Setup to PROG# LowData Hold after PROG#ENABLE High to VPPVPP Setup to PROG# LowVPP Hold after PROG#PROG# Width

4.048TOSC48TOSC48TOSC48TOSC48TOSC101090

110

µsµsµs

Min12.5

Max13.5756.0

UnitsD.C. VoltsmAMHz

SymbolVPPIPPFOSCTAVGLTGHAXTDVGLTGHDXTEHSHTSHGLTGHSLTGLGH34

PRELIMINARY

8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 18. Nonvolatile Memory Programming and Verification Characteristics at

TA = 21 – 27 °C, VCC = 5 V, and VSS = 0 V(Continued)

TAVQVAddress to Data ValidTELQVENABLE Low to Data ValidTEHQZData Float after ENABLETGHGL

PROG# High to PROG# Low

8.0ERRATA

There are no known errata for this product.

9.0REVISION HISTORY

This (-003) revision of the 8XC251SA/SB/SP/SQdatasheet contains information on products with“[M] [C] '94 '95 C” as the last line of the topsidemarking. This datasheet replaces earlier productinformation. The following changes appear in the -003 datasheet:1.Real-time wait state operation is described in the datasheet.

2.Memory map reserved locations are newly defined and the Memory Map is now referred to as the “Address Map.”

AC Characteristics have been updated. The following AC parameters have changed: TLLAX, TRLRH, TWLWH, TLLRL, TRLDV, TRHDZ1, TRHDZ2, TRHLH2, TTWHLH, TAVDV1, TAVDV2, TAVRL, TAVWL1, TAVWL2, 4.DC Characteristics have been updated. The QVWH, and TWHAX.

following DC specs have changed: I max, IPD max, IDL typical, I5.An I vs. Frequency graph is included.

DLCC typical, and ICC max.6.Process information is no longer contained in CCthe datasheet.

The section “Programming and Verifying Non-volatile Memory” has been deleted. See the 8XC251SA/SB/SP/SQ Embedded Microcon-troller User’s Manual. Timing and Characteris-tics for Programming and Verifying Nonvolatile

PRELIMINARY

48TOSC48TOSC048TOSC

µs

memory have been retained in this datasheet.8.Signature Byte information has been deleted. See the 8XC251SA/SB/SP/SQ Embedded Microcontroller User’s Manual.

9.Sections in the datasheet are numbered.10.

New sections have been created to provide better organization. These include “Nomencla-ture,” “Pinout,” “Signals,” “Address Map,” “Electrical Characteristics,” “Thermal Charac-teristics,” “Nonvolatile Memory Programming and Verification Characteristics”, “Errata,” and “Revision History”

11.Proliferation Options and Package Options are in the Nomenclature section.

12.Temperature range is contained in the Electri-cal Characteristics section under “Operating Conditions”

13.

Bus timing diagrams have been organized into subsections.

The (-002) revision of the 8XC251SA/SB/SP/SQdatasheet contains information on products with“[M] [C] '94 '95 B” as the last line of the topsidemarking. This datasheet replaces earlier productinformation. The following changes appear in the -002 datasheet:1.A corrected PDIP diagram appears on page 7.2.A corrected formula to calculate Tdescribed on page 17.

LHLL is 3.

The RD#/PSEN# waveform is changed in Fig-ure 11 on page 25.

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