P87C251SB16资料

Commercial/Express

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Real Time and Programmed Wait State Bus Operation

Binary-code Compatible with MCS® 51Pin Compatible with 44-lead PLCC and 40-lead PDIP MCS 51 Sockets

Register-based MCS® 251 Architecture—40-byte Register File

—Registers Accessible as Bytes, Words, and Double WordsEnriched MCS 51 Instruction Set

—16-bit and 32-bit Arithmetic and Logic Instructions

—Compare and Conditional Jump Instructions

—Expanded Set of Move InstructionsLinear Addressing

256-Kbyte Expanded External Code/Data Memory Space

ROM/OTPROM/EPROM Options:

16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or without ROM/OTPROM/EPROM16-bit Internal Code Fetch-Kbyte Extended Stack SpaceOn-chip Data RAM Options:

1-Kbyte (SA/SB) or 512-Byte (SP/SQ) 8-bit, “Min” 2-clock External Code Fetch in

Page Mode

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User-selectable Configurations:

—External Wait States (0-3 wait states)—Address Range & Memory Mapping—Page Mode

32 Programmable I/O LinesSeven Maskable Interrupt Sources with Four Programmable Priority Levels

Three Flexible 16-bit Timer/countersHardware Watchdog TimerProgrammable Counter Array—High-speed Output

—Compare/Capture Operation—Pulse Width Modulator—Watchdog Timer

Programmable Serial I/O Port —Framing Error Detection

—Automatic Address RecognitionHigh-performance CHMOS TechnologyStatic Standby to 16-MHz OperationComplete System Development Support

—Compatible with Existing Tools—New MCS 251 Tools Available:

Compiler, Assembler, Debugger, ICEPackage Options (PDIP, PLCC, and Ceramic DIP)

Fast MCS 251 Instruction Pipeline

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This document contains information on products with “[M] [C] '94 '95 C” as the last line of the top marking diagram. A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code compatible with MCS 51 microcontrollers and pin compatible with 40-lead PDIP and 44-lead PLCC MCS 51 microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM. A variety of features can be selected by new user-programmable configurations.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor varia-tions to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 2004July 2004Order Number: 272783-004

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

System Bus and I/O PortsP0.7:0P2.7:0CodeOTPROM/ROM8 Kbytesor16 KbytesI/O Ports and Peripheral SignalsP1.7:0P3.7:0Port 0DriversPort 2DriversData RAM512 Bytesor1024 BytesPort 1DriversPort 3DriversMemory Data (16)WatchdogTimerPeripheralInterfaceTimer/CountersMemory Address (16)Bus InterfaceCode Bus (16)Code Address (24)Instruction SequencerData Address (24)InterruptHandlerIB Bus (8)PCASRC2 (8)Data Bus (8)SRC1 (8)ALURegisterFileDataMemoryInterfaceClock&ResetSerial I/OPeripheralsDST (16)MCS® 251 Microcontroller CoreClock & Reset8XC251SA/SB/SP/SQ MicrocontrollerA4214-01Figure 1. 8XC251SA/SB/SP/SQ Block Diagram 2

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TEMPERATURE RANGE

With the commercial (standard) temperature option, the device operates over the temperature range 0°C to +70°C. The express temperature option provides -40°C to +85°C device operation.

Quality and Reliability Handbook (order number 210997).

All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel’s PROLIFERATION OPTIONS

Table 1 lists the proliferation options. See Figure 2for the 8XC251SA/SB/SP/SQ family nomenclature.

Table 1. Proliferation Options

8XC251SA/SB/SP/SQ(0 – 16 MHz; 5 V ±10%)

80C251SB16CPU-only80C251SQ16CPU-only83C251SA16ROM83C251SB16ROM83C251SP16ROM83C251SQ16ROM

87C251SA16OTPROM/EPROM87C251SB16OTPROM/EPROM87C251SP16OTPROM/EPROM87C251SQ16

OTPROM/EPROM

PROCESS INFORMATION

This device is manufactured on a complimentary high-performance metal-oxide semiconductor (CHMOS) process. Additional process and reliability information is available in Intel’s Components

thermal impedance test methodology.

Table 2. Thermal CharacteristicsPackage TypeθJAθJC44-lead PLCC46°C/W16°C/W40-lead PDIP45°C/W16°C/W40-lead Ceramic DIP

30.5°C/W

10°C/W

PACKAGE OPTIONS

Table 3 lists the 8XC251SA/SB/SP/SQ packages.

Table 3. Package Information

Pkg.DefinitionTemperatureX 44 ld. PLCC0°C to +70°CX 40 ld. Plastic DIP0°C to +70°CX 40 ld. Ceramic DIP0°C to +70°CX 44 ld. PLCC-40°C to +85°CX40 ld. Plastic DIP

-40°C to +85°C

NOTE:

To address the fact that many of the pack-age prefix variables have changed, all package prefix variables in this document are now indicated with an \"x\".

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

XTeXX8XXXXXXXXXFigure 2. The 8XC251SA/SB/SP/SQ Family Nomenclature

Table 4. Description of Product Nomenclature

Parameter

Temperature and Burn-in Options

Optionsno markX

Packaging Options

XXX

Program Memory Options

037

Process InformationProduct Family

Device Memory Options

C251SASBSPSQ

Device Speed

16

Description

Commercial operating temperature range (0°C to 70°C) with Intel standard burn-in.

Express operating temperature range (-40°C to 85°C) with Intel standard burn-in.

44-lead Plastic Leaded Chip Carrier (PLCC)40-lead Plastic Dual In-line Package (PDIP)

40-lead Ceramic Dual In-line Package (Ceramic DIP)Without ROM/OTPROM/EPROMROM

User programmable OTPROM/EPROMCHMOS

8-bit control architecture

1-Kbyte RAM/8-Kbyte ROM/OTPROM/EPROM

1-Kbyte RAM/16-Kbyte ROM/OTPROM/EPROM or without ROM/OTPROM/EPROM

512-byte RAM/8-Kbyte ROM/OTPROM/EPROM

512-byte RAM/16-Kbyte ROM/OTPROM/EPROM or without ROM/OTPROM/EPROMExternal clock frequency

NOTES:

1.To address the fact that many of the package prefix variables have changed, all package prefix vari-ables in the document are now indicated with an \"x\".

edpee SvicDeilyamt FucnodoPratinsrmtionfoOps Iry esmoocPrmem-raogPrnsstioonOpptiin On-uring Bagndcke aPaturA2815-01empra4

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Table 5. 8XC251SA/SB/SP/SQ Memory Map

Internal Address)Description

Notes

FF:FFFFHFF:4000H External Memory (FF:FFF8H–FF:FFFFH are internally decoded for Configuration Byte data in all ROM/OTPROM/EPROM devices with EA# = 1. For all devices with EA# = 0, the last 8 bytes of the external address range FF:XFF8H–1, 3, 10

FF:XFFFH contain Configuration Byte information).

FF:3FFFH External memory or for internal ROM/OTPROM/EPROM devices: 16-Kbytes of

FF:0000Hinternal addresses as determined by the EA# pin (ROM/OTPROM/EPROM array addresses end at FF:1FFFH.Table 8). Note: 8-Kbyte internal 3, 4, 5FE:FFFFHFE:0000H External Memory3FD:FFFFH FD:0000HReserved6FC:FFFFHFC:0000H Reserved6FB:FFFFH04:0000H Reserved603:FFFFH 03:0000HReserved602:FFFFH02:0000H Reserved601:FFFFH01:0000H External Memory

300:FFFFH External memory or with EMAP# bit = 0 this address range for 16-Kbyte devices 00:E000His redirected to internal ROM/OTPROM/EPROM array region.5, 700:DFFFH00:0420H External Memory

700:041FH00:0080H On-chip RAM (512 byte RAM devices end at 00:021FH700:007FH 00:0020H On-chip RAM

800:001FH00:0000H

Storage for R0–R7 of Register File

2, 9

NOTES:

1.18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).

2.The special function registers (SFRs) and the register file have separate internal address spaces.3.Data in this area is accessible by indirect addressing only.

4.Devices can reset into different internal or external starting locations depending on the state of EA#

and configuration register information (see EA#. See also UCONFIG1:0 bit definitions).

5.The 16-Kbyte ROM/OTPROM/EPROM devices allow internal locations FF:2000H–FF:3FFFH to map

into region 00:. In this case, if EA# = 1, a data read to 00:E000H–00:FFFFH is redirected to internal ROM/OTPROM/EPROM (see bit 1 in UCONFIG0). This is not available for 8-Kbyte ROM/OTPROM/EPROM devices.

6.This reserved area returns unspecified values and writes no data. 7.Data is accessible by direct and indirect addressing.8.Data is accessible by direct, indirect, and bit addressing.

9.Data is accessible by direct, indirect, and register addressing.

10.Eight addresses at the top of all external memory maps are reserved for current and future device

configuration byte information.

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

8XC251SA/SB/SP/SQ 44-lead PLCC Package

P1.5 / CEX2P1.6 / CEX3 / WAIT#P1.7 / CEX4 / A17 / WCLKRSTP3.0 / RXDVCC2P3.1 / TXDP3.2 / INT0#P3.3 / INT1#P3.4 / T0P3.5 / T1710111213141516176543214443424140P1.4 / CEX1P1.3 / CEX0P1.2 / ECIP1.1 / T2EXP1.0 / T2VSS1VCCAD0 / P0.0AD1 / P0.1 AD2 / P0.2 AD3 / P0.38XC251SA8XC251SB8XC251SP8XC251SQView of component asmounted on PC board18192021222324252627283938373635343332313029AD4 / P0.4AD5 / P0.5AD6 / P0.6AD7 / P0.7EA# / VPPVSS2ALE / PROG#PSEN#A15 / P2.7A14 / P2.6A13 / P2.5P3.6 / WR# P3.7 / RD# / A16XTAL2XTAL1VSSVSS2A8 / P2.0A9 / P2.1A10 / P2.2A11 / P2.3A12 / P2.4A4205-02Figure 3. 8XC251SA/SB/SP/SQ 44-lead PLCC Package

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P1.0 / T2P1.1 / T2EXP1.2 / ECIP1.3 / CEX0P1.4 / CEX1P1.5 / CEX2P1.6 / CEX3 / WAIT#P1.7 / CEX4 / A17 / WCLKRSTP3.0 / RXDP3.1 / TXDP3.2 / INT0#P3.3 / INT1#P3.4 / T0P3.5 / T1P3.6 / WR#P3.7 / RD# / A16XTAL2XTAL1VSS1234567101112131415161718192040393837363534333231302928VCCAD0 / P0.0AD1 / P0.1AD2 / P0.2AD3 / P0.3AD4 / P0.4AD5 / P0.5AD6 / P0.6AD7 / P0.7EA# / VPPALE / PROG#PSEN#A15 / P2.7A14 / P2.6A13 / P2.5A12 / P2.4A11 / P2.3A10 / P2.2A9 / P2.1A8 / P2.08XC251SA8XC251SB8XC251SP8XC251SQView ofcomponentas mountedon PC board27262524232221A4206-03Figure 4. 8XC251SA/SB/SP/SQ 40-lead PDIP and Ceramic DIP Packages

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Table 6. PLCC/DIP Lead Assignments Listed by Functional Category

Address & DataName

PLCCDIPAD0/P0.04339AD1/P0.14238AD2/P0.24137AD3/P0.34036AD4/P0.43935AD5/P0.53834AD6/P0.63733AD7/P0.73632A8/P2.02421A9/P2.12522A10/P2.22623A11/P2.32724A12/P2.42825A13/P2.52926A14/P2.63027A15/P2.73128P3.7/RD#/A161917P1.7/CEX4/A17/WCLK

9

8

Processor ControlName

PLCCDIPP3.2/INT0#1412P3.3/INT1#1513EA#/VPP3531RST109XTAL12118XTAL2

20

19

8

Input/OutputName

PLCCDIPP1.0/T221P1.1/T2EX32P1.2/ECI43P1.3/CEX054P1.4/CEX165P1.5/CEX276P1.6/CEX3/WAIT#87P1.7/CEX4/A17/WCLK98P3.0/RXD1110P3.1/TXD1311P3.4/T01614P3.5/T1

17

15

Power & GroundName

PLCCDIPVCC4440

VCC212VSS2220VSS11VSS2

23, 34EA#/VPP

35

31Bus Control & StatusName

PLCCDIPP3.6/WR#1816P3.7/RD#/A161917ALE/PROG#3330PSEN#

32

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Table 7. Lead Assignments Arranged by Lead Number

PLCCDIP

Name

1VSS121P1.0/T232P1.1/T2EX43P1.2/ECI54P1.3/CEX065P1.4/CEX176P1.5/CEX287P1.6/CEX3/WAIT#98P1.7/CEX4/A17/WCLK109RST1110P3.0/RXD12VCC21311P3.1/TXD1412P3.2/INT0#1513P3.3/INT1#1614P3.4/T01715P3.5/T11816P3.6/WR#1917P3.7/RD#/A162018XTAL22119XTAL122

20VSS

PLCCDIP

Name

23VSS22421A8/P2.02522A9/P2.12623A10/P2.22724A11/P2.32825 A12/P2.42926A13/P2.53027A14/P2.63128A15/P2.73229PSEN#3330ALE/PROG#34VSS23531EA#/VPP3632AD7/P0.73733AD6/P0.63834AD5/P0.53935AD4/P0.44036AD3/P0.34137AD2/P0.24238AD1/P0.14339AD0/P0.044

40VCC

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SIGNAL DESCRIPTIONS

Table 8. Signal Descriptions

Signal NameA17

TypeO

Description

Alternate Function

18th Address Bit (A17). Output to memory as 18th external address P1.7/CEX4/bit (A17) in extended bus applications, depending on the values of bits WCLKRD0 and RD1 in configuration byte UCONFIG0 (see Table 9). See also RD# and PSEN#.

Address Line 16. See RD#.

Address Lines. Upper address lines for the external bus.

Address/Data Lines. Multiplexed lower address lines and data lines for external memory.

Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus.

Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode.

RD#P2.7:0P0.7:0PROG#

A16A15:8†AD7:0†ALE

OOI/OO

CEX4:0I/O

P1.6:3 P1.7/A17/ WAIT#

EA#I

External Access. Directs program memory accesses to on-chip or off-VPPchip code memory. For EA# = 0, all program memory accesses are off-chip. For EA# = 1, an access is to on-chip ROM/OTPROM/EPROM if the address is within the range of the on-chip

ROM/OTPROM/EPROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without on-chip

ROM/OTPROM/EPROM, EA# must be strapped to ground.PCA External Clock Input. External clock input to the 16-bit PCA timer.

External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#.

Programming Pulse. The programming pulse is applied to this pin for programming the on-chip OTPROM.

Port 0. This is an 8-bit, open-drain, bidirectional I/O port.Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.

P1.2P3.3:2

ECIINT1:0#

II

PROG#P0.7:0P1.0 P1.1 P1.2 P1.7:3

II/OI/O

ALEAD7:0T2 T2EX ECI CEX3:0 CEX4/A17/ /WAIT#/ WCLKA15:8

P2.7:0

†

I/OPort 2. This is an 8-bit, bidirectional I/O port with internal pullups.

The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-patible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).

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Table 8. Signal Descriptions (Continued)

Signal NameTypeDescription

Alternate FunctionP3.0 I/O

Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.

RXD P3.1P3.3:2 TXDINT1:0# P3.5:4P3.6 T1:0P3.7 WR# RD#/A16 PSEN#

O

Program Store Enablefor a memory address range that depends on bits RD0 and RD1 in . Read signal output. This output is asserted —

configuration byte UCONFIG0 (see RD# and Table 9):

RD#ORead or 17th Address Bit (A16). memory or 17th external address bit (A16), depending on the values of Read signal output to external data P3.7/A16

bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN# and ):

RSTIResetperiods while the oscillator is running resets the device. The port pins . Reset input to the chip. Holding this pin high for oscillator —

are driven to their reset conditions when a voltage greater than Vapplied, whether or not the oscillator is running. This pin has an inter-IH1 is nal pulldown resistor, which allows the device to be reset by connect-ing a capacitor between this pin and VCC.

Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation.

RXDI/OReceive Serial Data0 and receives data in serial I/O modes 1, 2, and 3.

. RXD sends and receives data in serial I/O mode P3.0T1:0I Timer 1:0 External Clock Inputs. When timer 1:0 operates as a P3.5:4counter, a falling edge on the T1:0 pin increments the count.

T2

I/O

Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal P1.0

is the external clock input. For the clock-out mode, it is the timer 2 clock output.

T2EXITimer 2 External Input. In timer 2 capture mode, a falling edge ini-P1.1

tiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. In the up-down counter mode, this signal determines count direction: 1=up, 0=down.

TXDOTransmit Serial Dataand transmits serial data in serial I/O modes 1, 2, and 3.. TXD outputs the shift clock in serial I/O mode 0 P3.1VCCPWR Supply Voltage. Connect this pin to the +5V supply voltage.

—VCC2

PWR

Secondary Supply Voltage 2.vided to reduce power supply noise. Connection of this pin to the +5V This supply voltage connection is pro-—

supply voltage is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, Vnected without loss of compatibility. (Not available on DIP)

SS2 can be uncon-VPPIProgramming Supply Voltage. The programming supply voltage is EA#applied to this pin for programming the on-chip OTPROM/EPROM.VSS

GND

Circuit Ground. Connect this pin to ground.

—

†

The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-patible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 8. Signal Descriptions (Continued)

Signal NameVSS1

TypeGND

Description

Secondary Ground. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SA/SB/SP/SQ as a pin-for-pin replacement for the 8XC51BH, VSS1 can be unconnected without loss of compatibility. (Not available on DIP)

Secondary Ground 2. This ground is provided to reduce ground

bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP)

Real Time Wait State Input. The real time WAIT# input is enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus cycles, the external memory system can signal ‘system ready’ to the microcontroller in real time by controlling the WAIT# input signal on the port 1.6 input.

Wait Clock Output. The real time WCLK output is driven at port 1.7 (WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H. When enabled, the WCLK output produces a square wave signal with a period of one-half the ocillator frequency.Write. Write signal output to external memory.

Input to the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing.

Output of the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected.

Alternate Function—

VSS2

GND—

WAIT#IP1.6/CEX3

WCLKO

P1.7/CEX4/A17

WR#XTAL1

OI

P3.6—

XTAL2

†

O—

The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-patible with 44-lead PLCC and 40-lead DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).

Table 9. Memory Signal Selections (RD1:0)

RD1:00 00 11 01 1

P1.7/CEX/A17A17P1.7/CEX4P1.7/CEX4P1.7/CEX4

RD# RD# = A16RD# = A16P3.7 onlyAsserted for ≤ 7F:FFFFH

PSEN#Asserted for all addressesAsserted for all addressesAsserted for all addressesAsserted for ≥ 80:0000H

WR#

Asserted for writes to all memory locationsAsserted for writes to all memory locationsAsserted for writes to all memory locationsAsserted for all compati-ble MCS 51 memory locations

Features256-Kbyte external memory

128-Kbyte external memory

One additional port pin

Compatible with MCS 51 microcon-trollers

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ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS†

Ambient Temperature under Bias:

Commercial..........................................0°C to +70°CExpress.............................................-40°C to +85°CStorage Temperature ..............................-65°C to +150°CVoltage on EA#/VPP Pin to VSS.................. 0 V to +13.0 VVoltage on Any other Pin to VSS.............. -0.5 V to +6.5 VIOL per I/O Pin..........................................................15 mAPower Dissipation................................................... 1.5 W

NOTE:

Maximum power dissipation is based on package heat-transfer limitations, not device power consumption.OPERATING CONDITIONS†

TA (Ambient Temperature Under Bias):

Commercial..........................................0°C to +70°CExpress.............................................-40°C to +85°CVCC (Digital Supply Voltage) ...................... 4.5 V to 5.5 VVSS .............................................................................. 0 V

NOTICE: This document contains informa-tion on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales Office that you have the latest datasheet before finaliz-ing a design.

†WARNING: Stressing the device beyond the “Absolute

Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.

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D.C. Characteristics

Parameter values apply to all devices unless otherwise indicated.

Table 10. DC Characteristics at VCC = 4.5 – 5.5 V

SymbolVILVIL1VIHVIH1VOL

ParameterInput Low Voltage (except EA#)Input Low Voltage (EA#)

Input High Voltage (except XTAL1, RST)Input High Voltage (XTAL1, RST)Output Low Voltage (Port 1, 2, 3)

Min-0.500.2VCC + 0.90.7VCC

Typical

Max0.2VCC – 0.10.2VCC – 0.3VCC + 0.5VCC + 0.50.30.451.00.30.451.0

VCC – 0.3VCC – 0.7VCC – 1.5

UnitsVVVVV

IOL = 100 µA IOL = 1.6 mA IOL = 3.5 mA(Note 1, Note 2)IOL = 200 µAIOL = 3.2 mAIOL = 7.0 mA(Note 1, Note 2)IOH = -10 µAIOH = -30 µAIOH = -60 µA(Note 3)

Test Conditions

VOL1

Output Low Voltage (Port 0, ALE, PSEN#)

V

VOH

Output High Voltage (Port 1, 2, 3, ALE, PSEN#)

V

NOTES:

1.Under steady-state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:10 mAMaximum IOL per 8-bit port:

port 026 mA ports 1–315 mAMaximum Total IOL for

all output pins

71 mA

If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.2.

Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive load-ing exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qual-ify ALE or other signals with a Schmitt trigger or CMOS-level input logic.

Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-tion when the address lines are stabilizing.

Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.

3.4.

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Table 10. DC Characteristics at VCC = 4.5 – 5.5 V (Continued)

SymbolVOH1

ParameterOutput High Voltage (Port 0 in External Address)

Output High Voltage (Port 2 in External Address during Page Mode)

Logical 0 Input Cur-rent (Port 1, 2, 3)Input Leakage Cur-rent (Port 0)

Logical 1-to-0 Transi-tion Current (Port 1, 2, 3)

RST Pulldown Resis-tor

Pin CapacitancePowerdown Current Idle Mode Current Operating Current

40

10 (Note 4)10(Note 4)5(Note 4)20(Note 4)

< 20745

MinVCC – 0.3VCC – 0.7VCC – 1.5VCC – 0.3 VCC – 0.7 VCC – 1.5

-50+/-10-650

Typical

Max

UnitsV

Test ConditionsIOH = -200 µAIOH = -3.2 mAIOH = -7.0 mAIOH = -200 µA IOH = -3.2 mAIOH = -7.0 mA VIN = 0.45 V0.45 < VIN < VCCVIN = 2.0 V

Voh2

V

IILILIITL

µAµAµA

RrstCioIpdIdlICC

225kΩpFµAmAmA

FOSC = 16 MHzFOSC = 16 MHzFOSC = 16 MHzTA = 25 °C

NOTES:

1.Under steady-state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin:10 mAMaximum IOL per 8-bit port:

port 026 mA ports 1–315 mAMaximum Total IOL for

all output pins

71 mA

If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.2.

Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive load-ing exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qual-ify ALE or other signals with a Schmitt trigger or CMOS-level input logic.

Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN# to drop below the specifica-tion when the address lines are stabilizing.

Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed.

3.4.

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

VCCVCCP0RST8XC251SA8XC251SB8XC251SP8XC251SQ(NC)XTAL2XTAL1VSSEA#IPDVCCAll other 8XC251SA/SB/SP/SQ pins are unconnected.A4208-01Figure 5. IPD Test Condition, Powerdown Mode, VCC = 2.0 – 5.5V

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A.C. Characteristics

Table 11 lists AC timing parameters for the 8XC251SA/SB/SP/SQ with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and/or by extending ALE. In the table, Notes 3 and 5 mark parameters affected by an

ALE wait state, and Notes 4 and 5 mark parameters affected by a PSEN#/RD#/WR# wait state.

Figures 6–11 show the bus cycles with the timing parameters.

Table 11. AC Characteristics (Capacitive Loading = 50 pF)

SymbolFOSCTosc

Parameter

XTAL1 Frequency1/FOSC

@ 12 MHz @ 16 MHzALE Pulse Width

@ 12 MHz @ 16 MHzAddress Valid to ALE Low

@ 12 MHz @ 16 MHzAddress Hold after ALE Low

@ 12 MHz @ 16 MHz RD# or PSEN# Pulse Width

@ 12 MHz @ 16 MHzWR# Pulse Width

@ 12 MHz @ 16 MHz

ALE Low to RD# or PSEN# Low

@ 12 MHz @ 16 MHzALE High to Address Hold

@ 12 MHz @ 16 MHz

@ Max Fosc (1)MinN/AN/A

MaxN/AN/A

Fosc VariableMin083.362.5

Max16

UnitsMHzns

Tlhll

73.3 52.5 63.3 42.5 10 10

156.6 115

156.6 115 63.3 42.5 83.3 62.5

(1+2M) TOSC – 10(1+2M) TOSC – 2010

ns(3)ns(3)ns

Tavll

Tllax

TRLRH (2)

2(1+N)TOSC – 102(1+N)TOSC – 10TOSC – 20

ns(4)ns(4)ns

Twlwh

Tllrl (2)

Tlhax

(1+2M)TOSC

ns(3)

NOTES:

1.16 MHz.

2.Specifications for PSEN# are identical to those for RD#.3.In the formula, M=Number of wait states (0 or 1) for ALE.

4.In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#5.“Typical” specifications are untested and not guaranteed.

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Table 11. AC Characteristics (Capacitive Loading = 50 pF) (Continued)

Symbol

Parameter

@ Max Fosc (1)Min

Max

116.6 750Typ.=0 2(5)

10 10

176.6 135

10 10176.6 135176.6 135

263.2 180

278.2 195

116.6 75

0Typ. = 0 (5)

2

Fosc VariableMin

Max

Unitsns(4)

TRLDV (2)RD#/PSEN# Low to valid Data/Instruction In

@ 12 MHz @ 16 MHzTRHDX (2)Data/Instruction Hold Time. Occurs after

RD#/PSEN# are exerted to VOH TRLAZ (2)Trhdz1

RD#/PSEN# Low to Address FloatInstruction Float after RD#/PSEN# High

@ 12 MHz @ 16 MHzData Float after RD#/PSEN# High

@ 12 MHz @ 16 MHz

RD#/PSEN# High to ALE High (Instruction)

@ 12 MHz @ 16 MHzRD#/PSEN# High to ALE High (Data)

@ 12 MHz @ 16 MHzWR# High to ALE High

@ 12 MHz @ 16 MHz

Address (P0) Valid to Valid Data/Instruction In

@ 12 MHz @ 16 MHzAddress (P2) Valid to Valid Data/Instruction In

@ 12 MHz @ 16 MHzAddress (P0) Valid to Valid Instruction In

@ 12 MHz @ 16 MHz

2(1+N)Tosc – 50

nsnsns

10

ns

2Tosc +10

ns

Trhdz2

Trhlh1

10

ns

2Tosc + 10

ns

2Tosc + 10

ns(3)ns(3) ns

2TOSC – 50

TRHLH2

TWHLH

Tavdv1

4(1+M/2)TOSC – 704(1+M/2)TOSC – 55

Tavdv2

TAVDV3

NOTES:

1.16 MHz.

2.Specifications for PSEN# are identical to those for RD#.3.In the formula, M=Number of wait states (0 or 1) for ALE.

4.In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#5.“Typical” specifications are untested and not guaranteed.

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Table 11. AC Characteristics (Capacitive Loading = 50 pF) (Continued)

SymbolTavrl (2)

Parameter

Address Valid to RD#/PSEN# Low

@ 12 MHz @ 16 MHzAddress (P0) Valid to WR# Low

@ 12 MHz @ 16 MHzAddress (P2) Valid to WR# Low

@ 12 MHz @ 16 MHzData Hold after WR# High

@ 12 MHz @ 16 MHzData Valid to WR# High

@ 12 MHz @ 16 MHzWR# High to Address Hold

@ 12 MHz @ 16 MHz

@ Max Fosc (1)Min

146.6 105

156.6 115

166.6 125 63.3 42.5

143.6 102

146.6 105

Max

Fosc VariableMin

Max

Unitsns(3)ns(3)ns(3)ns

TOSC – 20

ns(4)ns

2TOSC – 20

2(1+M)TOSC – 202(1+M)TOSC – 102(1+M)TOSC

Tavwl1

TAVWL2

TWHQX

TQVWH

2(1+N)TOSC – 23

TWHAX

NOTES:

1.16 MHz.

2.Specifications for PSEN# are identical to those for RD#.3.In the formula, M=Number of wait states (0 or 1) for ALE.

4.In the formula, N=Number of wait states (0,1,2, or 3) for RD#/PSEN#/WR#5.“Typical” specifications are untested and not guaranteed.

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

SYSTEM BUS TIMINGS

TOSCXTAL1ALETLHLL†TRLRH†TLLRL†TRHLH2RD#/PSEN#TRLDV†TRLAZTLHAX†TAVLL†P0TRHDZ2TLLAXTRHDXD7:0Data InA7:0TAVRL†TAVDV1†TAVDV2†P2/A16/A17A15:8/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics.A4210-01Figure 6. External Read Data Bus Cycle in Nonpage Mode

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TOSCXTAL1ALETLHLL†TLLRL†TRLRH†TRHLH1RD#/PSEN#TRLDV†TRLAZTLHAX†TAVLL†P0TLLAXTRHDZ1TRHDXD7:0Instruction InA7:0TAVRL†TAVDV1†TAVDV2†P2/A16/A17A15:8/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics.A4211-01Figure 7. External Instruction Bus Cycle in Nonpage Mode

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

TOSCXTAL1ALETLHLL†TWLWH†WR#TLHAX†TAVLL†TLLAXP0A7:0TAVWL1†TAVWL2†A15:8/A16/A17TWHLHTQVWHTWHQXD7:0Data OutTWHAXP2/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics.A4179-01Figure 8. External Write Data Bus Cycle in Nonpage Mode

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TOSCXTAL1ALETLHLL†TLLRL†TRLRH†TRHLH2TRLDV†TRLAZRD#/PSEN#TLHAX†TAVLL†P2TRHDZ2TLLAXTRHDXD7:0Data InA15:8TAVRL†TAVDV1†TAVDV2†P0/A16/A17A7:0/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics. A4212-01Figure 9. External Read Data Bus Cycle in Page Mode

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

TOSCXTAL1ALETLHLL†TWLWH†WR#TLHAX†TAVLL†TLLAXP2A15:8TAVWL1†TAVWL2†A7:0/A16/A17TWHLHTQVWHTWHQXD7:0Data OutTWHAXP0/A16/A17† The value of this parameter depends on wait states. See the table of AC characteristics. A4182-01Figure 10. External Write Data Bus Cycle in Page Mode

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TOSCXTAL1ALETLHLL†TLLRL†RD#/PSEN#TRLDV†TRLAZTLHAX†TAVLL†P2TLLAXD7:0Instruction InTAVDV3A7:0/A16/A17Page Hit††TRHDZ1TRHDXD7:0Instruction In†††A15:8TAVRL†TAVDV1†TAVDV2†P0/A16/A17A7:0/A16/A17Page Miss††† The value of this parameter depends on wait states. See the table of AC characteristics.†† A page hit (i.e., a code fetch to the same 256-byte \"page\" as the previous code fetch) requires one state (2TOSC); a page miss requires two states (4TOSC).††† During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle. A4213-02Figure 11. External Instruction Bus Cycle in Page Mode

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

AC Characteristics — Serial Port, Shift Register Mode

Table 12. Serial Port Timing — Shift Register Mode

SymbolTXLXLTQVSHTXHQXTXHDXTXHDV

Parameter

Serial Port Clock Cycle Time

Output Data Setup to Clock Rising EdgeOutput Data hold after Clock Rising EdgeInput Data Hold after Clock Rising EdgeClock Rising Edge to Input Data Valid

Min12TOSC10TOSC – 1332TOSC – 117

0

10TOSC – 133

Max

Unitsnsnsnsnsns

TXLXLTXDTXHQXTQVXH0TXHDV123456Set TI†7RXD(Out)TXHDXValidValidTAV†Set RI†ValidValidValidValidRXD(In)ValidValid†TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.A2592-02Figure 12. Serial Port Waveform — Shift Register Mode

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External Clock Drive

Table 13. External Clock Drive

Symbol1/TCLCLTCHCXTCLCXTCLCHTCHCL

Parameter

Oscillator Frequency (FOSC)

High TimeLow TimeRise TimeFall Time

2020

1010

Min

Max16

UnitsMHznsnsnsns

TCLCHVCC – 0.50.7 VCC TCHCXTCLCX0.45 V0.2 VCC – 0.1 TCHCLTCLCLA4119-01Figure 13. External Clock Drive Waveforms

InputsVCC – 0.50.45 VOutputs0.2 VCC + 0.90.2 VCC – 0.1VIH MINVOL MAXAC inputs during testing are driven at VCC – 0.5V for a logic 1and 0.45 V for a logic 0. Timing measurements are made at a min of VIH for a logic 1 and VOL for a logic 0.A4118-01Figure 14. AC Testing Input, Output Waveforms

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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER

VLOAD + 0.1 VVLOADVLOAD – 0.1 VTiming ReferencePointsVOH – 0.1 VVOL + 0.1 VFor timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to floatwhen a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = ± 20 mA.A4117-01Figure 15. Float Waveforms

VCCAddress(16 Bits)A0 - A7P38XC251SA8XC251SB8XC251SP8XC251SQVCCRSTP2A8 - A15P1Data(8 Bits)ProgrammingSignalsEA#/VppXTAL1ALE/PROG#PSEN#4 MHzto6 MHzXTAL2VSSP0Program/Verify Mode(8 Bits)A4209-01Figure 16. Setup for Programming and Verifying Nonvolatile Memory

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PROGRAMMING AND VERIFYING NONVOLATILE MEMORY

The 87C251SA/SB/SP/SQ has several areas of nonvolatile memory that can be programmed and/or verified: on-chip code memory (16 Kbytes), lock bits (3 bits), encryption array (128 bytes), and signature bytes (3 bytes). The 8XC251SA/SB/SP/SQ User’s Manual (Order Number: 272795) provides procedures for programming and verifying the nonvolatile memory.

Figure 16 shows the setup for programming and/or verifying the nonvolatile memory. Table 14lists the programming and verification operations and indicates which operations apply to the different versions of the 87C251SA/SB/SP/SQ. It also specifies the signals on the programming input (PROG#) and the ports. The ROM/OTPROM/EPROM mode (port 0) specifies the operation (program or verify) and the base address of the memory area. The addresses (ports 1 and 3) are relative to the base address. (On-chip memory for an 8-Kbyte ROM/OTPROM/EPROM device is located at address range FF:0000H–FF:1FFFH. On-chip memory for a 16-Kbyte ROM/OTPROM/EPROM device is located at address range FF:0000H–FF:3FFFH. The other areas of the ROM/OTPROM/EPROM are outside the memory address space and are accessible only during programming and verification.)

Information in Figures 17 and 18 define the configuration bits. Figure 19 shows the waveforms for the programming and verification cycles, and Table 15 lists the timing specifica-tions. The signature bytes of the 83C251SA/SB/SP/SQ ROM versions and the 87C251SA/SB/SP/SQ OTP versions are factory programmed. Table 16 lists the addresses and the contents of the signature bytes.

Factory-programmed ROM and OTPROM versions of 8XC251SA/SB/SP/SQ use configu-ration byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQdevices without internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external application memory based on an internal address range of FF:FFF9:8H.

NOTE:

The VPP source in Figure 16 must be well regulated and free of glitches. The voltage on the Vspecified maximum, even under transient PP pin must not exceed the

conditions.

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Table 14. Programming and Verification Modes8XC251SA/SB/SP/SQX = 7

Program on-chip code memory

Verify on-chip code memory

Program configuration bytes

Verify configuration bytes

Program lock bitsVerify lock bitsProgram encryption array

Verify signature bytes

YYYY

YY

25 PulsesHigh25 PulsesHigh

6BH2BH6CH29H

XX DataDataData

0001H–0003H

0000H0000H–007FH0030H, 0031H, 0060H

YY

YX = 3

5 PulsesHigh

68H28H

DataData

Addresses P1 (high), P3 (low)0000H–3FFFH (16K)000H-1FFFH (8K)0000H–3FFFH (16K)0000H-1FFFH (8K)

221, 341

ModePROG#P0P2Notes1

NOTES:

1.The PROG# pulse waveform is shown in Figure 19.

2.Factory-programmed ROM, OTPROM and EPROM versions of 8XC251SA/SB/SP/SQ use config-uration byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQdevices without internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external application memory based on an internal address range of FF:FFF9:8H.

3.When programming the lock bits, the data bits on port 2 are don’t care. Identify the lock bits with

the address as follows: LB3 - 0003H, LB2 - 0002H, LB1 - 0001H

4.The three lock bits are verified in a single operation. The states of the lock bits appear simulta-neously at port 2 as follows: LB3 - P2.3, LB2 - P2.2. LB1 - P2.1. High = programmed.

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UCONFIG07UCONBit Number

7

WSA1#

WSA0#

XALE#

RD1

RD0

Address FF:FFF8H

0

PAGE#

SRC

Bit MnemonicUCON

Function

Configuration byte location selector:

Clearing this bit causes the device to fetch configuration information from on-chip memory. Setting this bit causes the device to locate configuration information based upon the state of EA# during reset (EA# = VCC = on-chip; EA# = VSS = off-chip).

Wait State Select (for all pages except 01H). WSA0# is identical to the WSA bit defined in the 8XC251SB A-step:WSA1#WSA0# Description 1 1 0 0

1 0 1 0

No wait states (01: page controlled by CONFIG1) Insert 1 wait state for all pages except the 01: page Insert 2 wait states for all pages except the 01: page Insert 3 wait states for all pages except the 01: page

6:5

WSA1#,WSA0#(see Note)

4XALE#

Extend Ale:

If this bit is set, the time of the ALE pulse is TOSC. Clearing this bit extends the time of the ALE pulse from TOSC to 3TOSC, which adds one external wait state. RD# and PSEN# function select:

RD1RD0RD# RangeP1.7/CEX4/A17 PSEN# Range 0 0 1 1

0 1 0 1

RD# = A16A17onlyAll Addresses RD# = A16P1.7/CEX4All Addresses P3.7 onlyP1.7/CEX4All Addresses ≤ 7F:FFFFHP1.7/CEX4≥ 80:0000H

3:2RD1, RD0

1PAGE#

Page Mode Select:

Clear this bit for page-mode (A15:8/D7:0 on P2, and A7:0 on P0). Set this bit for nonpage-mode (A15:8 on P2, and A7:0/D7:0 on P0 (compatible with MCS 51 microcontrollers)).

Source Mode/Binary Mode Select:

Set this bit for source mode. Clear this bit for binary mode (binary-code compatible with MCS 51 microcontrollers).

0SRC

Figure 17. Configuration Byte 0

NOTE:

Factory-programmed ROM, OTPROM and EPROM versions of 8XC251SA/SB/SP/SQ use configura-tion byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ devices without internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external application memory based on an internal address range of FF:FFF9:8H.

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.

UCONFIG17

—Bit Number7:54

—

—

INTR

WSB

WSB1#

Address FF:FFF9H

0

WSB0#

EMAP#

BitMnemonic

—INTR

Function

Reserved; set these bits when writing to UCONFIG1.

Interrupt Mode:

If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the PC register and the PSW1 register). If this byte is clear, interrupts push 2 bytes onto the stack (the 2 lower bytes of the PC register).

Wait State B. Only use this bit for A-step compatibility:

Clear this bit to generate one external wait state for memory region 01:. Set this bit for no wait states for region 01:.Wait States (01:XXXXH page only)WSB1#WSB0#Description

11100100

No wait states

Insert 1 wait state for the 01: page Insert 2 wait states for the 01: page Insert 3 wait states for the 01: page

3WSB

2:1

WSB1#, WSB0#

0EMAP#

EPROM MAP:

Clearing this bit maps the upper 8 Kbytes of on-chip code memory (FF:2000H–FF:3FFFH) to 00:E000H–00:FFFFH. If this bit is set, the upper 8 Kbytes of on-chip code memory are mapped only to FF:2000H–FF:3FFFH. If this bit is set mapping does not occur.

Figure 18. Configuration Byte 1

NOTE:

Factory-programmed ROM and OTPROM versions of 8XC251SA/SB/SP/SQ use configuration byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ devices without

internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external application memory based on an internal address range of FF:FFF9:8H.

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Programming CycleP1, P3Address (16 Bits)Verification CycleAddressTAVQVP2Data In (8 Bits)TDVGLTAVGLTGHGLTGHDXTGHAXData OutPROG#TGLGHTSHGLEA#/VPP12.75V5VTELQVTEHSHP0Mode (8 Bits)Mode A4128-0112345TGHSLTEHQZFigure 19. Timing for Programming and Verification of Nonvolatile Memory

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Table 15. Nonvolatile Memory Programming and Verification Characteristics at

TA = 21 – 27 °C, VCC = 5 V, and VSS = 0 V

SymbolVppIppFoscTAVGLTGHAXTDVGLTGHDXTEHSHTSHGLTGHSLTGLGHTAVQVTELQVTEHQZTGHGLNOTE:

Definition

Programming Supply VoltageProgramming Supply CurrentOscillator Frequency

Address Setup to PROG# LowAddress Hold after PROG#Data Setup to PROG# LowData Hold after PROG#ENABLE High to VPPVPP Setup to PROG# LowVPP Hold after PROG#PROG# WidthAddress to Data ValidENABLE Low to Data ValidData Float after ENABLEPROG# High to PROG# LowNotation for timing parameters:

D = DataS = Supply (VPP)

E = EnableV = Valid

G = PROG#X = No Longer Valid

H = HighZ = Floating

L = Low

0104.048TOSC48TOSC48TOSC48TOSC48TOSC101090

11048TOSC48TOSC48TOSC

µsµsµsµs

Min12.5

Max13.5756.0

UnitsD.C. VoltsmAMHz

A = Address Q = Data out

Table 16. Contents of the Signature Bytes

ADDRESS

30H31H60H60H60H60H60H60H60H60H61H

CONTENTS

H40H7AH7BH4AH4BHFAHFBHCAHCBH55H

DEVICE TYPE

Indicates Intel Devices

Indicates MCS251 core productIndicates 83C251SA deviceIndicates 83C251SB deviceIndicates 83C251SP deviceIndicates 83C251SQ deviceIndicates 87C251SA deviceIndicates 87C251SB deviceIndicates 87C251SP deviceIndicates 87C251SQ device

Indicates 8XC251SA/SB/SP/SQ B-step products

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Revision History

The following changes appear in the -004 datasheet:1.

To address the fact that many of the package prefix variables have changed, all package prefix variables in the document are now indicated with an \"x\".

The (-003) revision of the 8XC251SA/SB/SP/SQ datasheet contains information on products with “[M] [C] '94 '95 C” as the last line of the topside marking. This datasheet replaces earlier product information. The following changes appear in the -003 datasheet:1.2.3.

UCONFIG0.7 (UCON) is now defined.

Real time wait state operation is described in the datasheet.Memory map reserved locations are newly defined.

The (-002) revision of the 8XC251SA/SB/SP/SQ datasheet contains information on products with “[M] [C] '94 '95 B” as the last line of the topside marking. This datasheet replaces earlier product information. The following changes appear in the -002 datasheet:1.2.3.

A corrected PDIP diagram appears on page 7.

A corrected formula to calculate TLHLL is described on page 17.The RD#/PSEN# waveform is changed in Figure 11 on page 25.

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