Structure and method for latchup suppression

专利名称：Structure and method for latchup

suppression

发明人：Steven H. Voldman申请号：US10905878申请日：20050125公开号：US07282771B2公开日：20071016

专利附图：

摘要：A method and structure for an integrated circuit comprising a substrate of afirst polarity, a merged triple well region of a second polarity and a doped region of thesecond polarity abutting the well region. The doped region is adapted to suppress latch-

up in the integrated circuit. The doped region is placed under semiconductor devices ofthe first polarity and under the well region contact region. Additionally, the structuremay further include a deep trench (DT) structure and trench isolation (TI) structure tofurther improve latchup robustness.

申请人：Steven H. Voldman

地址：South Burlington VT US

国籍：US

代理机构：Greenblum & Bernstein, P.L.C.

代理人：Anthony J. Canale

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