P4C148-45PC资料

ULTRA HIGH SPEED 1K x 4STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)– 10/12/15/20/25/35/45/55 ns (Commercial)– 15/20/25/35/45/55 ns (P4C148 Military)Low Power Operation

Single 5V ± 10% Power Supply

Two Options

– P4C148 Low Power Standby Mode– P4C149 Fast Chip Select ControlCommon Input/Output PortsThree-State Outputs

Fully TTL Compatible Inputs and OutputsStandard Pinout (JEDEC Approved)– 18 Pin 300 mil DIP

– 18 Pin LCC (295 x 335 mil) [P4C148 only]– 18 Pin LCC (290 x 430 mil)

DESCRIPTION

The P4C148 and P4C149 are 4,096-bit ultra high-speedstatic RAMs organized as 1K x 4. Both devices havecommon input/output ports. The P4C148 enters thestandby mode when the chip enable (CE) goes HIGH;with CMOS input levels, power consumption is extremelylow in this mode. The P4C149 features a fast chip selectcapability using CS. The CMOS memories require noclocks or refreshing, and have equal access and cycletimes. Inputs are fully TTL-compatible. The RAMsoperate from a single 5V ± 10% tolerance power supply.

Access times as fast as 10 nanoseconds are available,permitting greatly enhanced system operating speeds.CMOS is used to reduce power consumption whenactive; for the P4C148, consumption is further reduced inthe standby mode.

The P4C148 and P4C149 are available in 18-pin 300 milDIP packages, as well as 2 different LCC packages,providing excellent board level densities.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

P4C148 DIP (C9, D1, P1)

P4C149 DIP (P1)

Document # SRAM104 REV B

1

Revised April 2007

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P4C148/P4C149

MAXIMUM RATINGS(1)

SymbolVCC

ParameterPower Supply Pin withRespect to GNDTerminal Voltage withRespect to GND(up to 7.0V)

Operating Temperature

Value–0.5 to +7–0.5 toVCC +0.5–55 to +125

UnitV

SymbolTBIASTSTGPTIOUT

ParameterTemperature UnderBias

Storage TemperaturePower DissipationDC Output Current

Value–55 to +125–65 to +150

1.050

Unit°C°CWmA

VTERMTA

V°C

RECOMMENDED OPERATINGCONDITIONS

Grade(2)CommercialMilitary

Ambient Temp0°C to 70°C-55°C to +125°C

Gnd0V0V

VCC

5.0V ± 10%5.0V ± 10%

CAPACITANCES(4)

(VCC = 5.0V, TA = 25°C, f = 1.0MHz)SymbolCINCOUT

ParameterInput Capacitance

ConditionsTyp.UnitVIN = 0V

57

pFpF

Output CapacitanceVOUT= 0V

DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage (2)Sym.VOHVOLVIHVILILIILOISBISB1

Parameter

Output High Voltage(TTL Load)Output Low Voltage(TTL Load)Input High VoltageInput Low VoltageInput Leakage CurrentOutput Leakage Current

VCC = Max., VIN = GND to VCCVCC = Max., CE, CS = VIH,VOUT = GND to VCC

Mil.Comm’lMil.Comm’lMil.Comm’lMil.Comm’l

Test Conditions

IOH = –4 mA, VCC = Min.IOL = +8 mA, VCC = Min

2.2–0.5(3)–10–5–10–5P4C148Min.2.4

0.4VCC+0.50.8+10+5+10+530231510

2.2–0.5(3)–10–5–10–5

Max.

P4C149Min.2.4

0.4VCC+0.50.8+10+5+10+5N/AN/AN/AN/AMax.

UnitVVVVµAµAmAmA

Standby Power SupplyCE ≥ VIH, VCC = Max.,Current (TTL Input Levels)f=Max., Outputs OpenStandby Power SupplyCurrent

(CMOS Input Levels)

CE ≥ VHC, VCC = Max., f= 0,Outputs Open

VIN ≤ 0.2V or VIN ≥ VCC –0.2V

N/A = Not Applicable

POWER DISSIPATION CHARACTERISTICS VS. SPEED

SymbolParameterICC

Dynamic Operating Current

Temperature RangeCommercialMilitary

-10-12-15-20-25-35-45-55Unit13013012011510010095

95

mA

N/AN/A145135125120115115mA

Document # SRAM104 REV BPage 2 of 10

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P4C148/P4C149

AC CHARACTERISTICS—READ CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)

SymtRCtAAtACtACtOHtLZtHZtRCStRCHtPUtPDParameterRead Cycle TimeAddress Access TimeChip Enable Access Time (P4C148)Chip Enable Access Time (P4C149)Output Hold from Address ChangeChip Enable to Output in Low Z (P4C149)Chip Disable to Output in High Z (P4C149)Read Command Setup TimeRead Command Hold TimeChip Enable to Power Up Time (P4C148)Chip Disable to Power Down Time (P4C148)0001032400012-10-12-15-20-25-35-45-55MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMax1012152025354555101083250001512121032600020151512328000252020143210000352525153214000453535203218000554545203220555525TIMING WAVEFORM OF READ CYCLE

TIMING WAVEFORM OF READ CYCLE NO. 2(6)

Notes:

1.Stresses greater than those listed under MAXIMUM RATINGS maycause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any otherconditions above those indicated in the operational sections of thisspecification is not implied. Exposure to MAXIMUM rating condi-tions for extended periods may affect reliability.

2.Extended temperature operation guaranteed with 400 linear feetper minute of air flow.

3.Transient inputs with VIL and IIL not more negative than –3.0V and

Document # SRAM104 REV BPage 3 of 10

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P4C148/P4C149

AC CHARACTERISTICS—WRITE CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9)

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE/CS CONTROLLED)(9)

Notes:

9.CE and WE must be LOW for WRITE cycle.

10.If CE goes HIGH simultaneously with WE high, the output remains in a high impedance state.11.Write Cycle Time is measured from the last valid address to the first transition address.

Document # SRAM104 REV BPage 4 of 10

AC TEST CONDITIONS

Input Pulse LevelsGND to 3.0V

Input Rise and Fall Times3nsInput Timing Reference Level1.5VOutput Timing Reference Level1.5V

Output Load

See Figures 1 and 2

Figure 1. Output Load

* including scope and test fixture.

Note:

Due to the ultra-high speed of the P4C148/149, care must be takenwhen testing this device; an inadequate setup can cause a normalfunctioning part to be rejected as faulty. Long high-inductance leads thatcause supply bounce must be avoided by bringing the VCC and groundplanes directly up to the contactor fingers. A 0.01 µF high frequency

Document # SRAM104 REV BP4C148/P4C149

TRUTH TABLE

ModeCEWEOutputPowerStandbyHXHigh ZStandbyReadLHDOUTActiveWrite

L

L

High Z

Active

Figure 2. Thevenin Equivalent

capacitor is also required between VCC and ground. To avoid signalreflections, proper termination must be used; for example, a 50Ω testenvironment should be terminated into a 50Ω load with 1.73V (TheveninVoltage) at the comparator input, and a 116Ω resistor must be used inseries with DOUT to match 166Ω (Thevenin Resistance).

Page 5 of 10

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P4C148/P4C149

ORDERING INFORMATION

SELECTION GUIDE

The P4C148/P4C149 are available in the following temperature, speed and package options.

Temperature RangeCommercial TemperatureMilitary TemperaturePackagePlastic DIPSide Brazed DIPCERDIPSide Brazed DIPLCC (290 x 430 mil)LCC (295 x 335 mil)CERDIPMilitary Processed*Side Brazed DIPLCC (290 x 430 mil)LCC (295 x 335 mil)Speed (ns)10-10PC-10CCN/AN/AN/AN/AN/AN/AN/AN/A12-12PC-12CCN/AN/AN/AN/AN/AN/AN/AN/A15-15PC-15CC-15DM-15CM-15LM-15LSM-15DMB-15CMB-15LMB-15LSMB20-20PC-20CC-20DM-20CM-20LM-20LSM-20DMB-20CMB-20LMB-20LSMB25-25PC-25CC-25DM-25CM-25LM-25LSM-25DMB-25CMB-25LMB-25LSMB35-35PC-35CC-35DM-35CM-35LM-35LSM-35DMB-35CMB-35LMB-35LSMB45-45PC-45CC-45DM-45CM-45LM-45LSM-45DMB-45CMB-45LMB55-55PC-55CC-55DM-55CM-55LM-55LSM-55DMB-55CMB-55LMB-45LSMB-55LSMB* Military temperature range with MIL-STD-883, Class B processing.N/A = Not Available

Document # SRAM104 REV BPage 6 of 10

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Pkg #C9# Pins18 (300 Mil)SymbolMinMaxA-0.200b0.0140.026b20.0300.065C0.0080.018D-0.960E0.2200.320eA0.300 BSCe0.100 BSCL0.1250.200Q0.0150.070S10.005-S20.005-Pkg #D1# Pins18 (300 Mil)SymbolMinMaxA-0.200b0.0140.026b20.0450.065C0.0080.018D-0.960E0.2200.310eA0.300 BSCe0.100 BSCL0.1250.200Q0.0150.070S10.005-α0°15°Document # SRAM104 REV BP4C148/P4C149

SIDE BRAZED DUAL IN-LINE PACKAGES

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P4C148/P4C149

Pkg #L7# Pins18SymbolMinMaxA0.0600.075A10.0500.065B10.0220.028D0.2800.305D1.150 BSCD2.075 BSCD3-0.305E0.4170.440E10.200 BSCE20.100 BSCE3-0.440e0.050 BSCh0.040 REFj0.020 REFL0.0450.055L10.0750.090L20.0750.148ND4NE5Pkg #L7-1# Pins18SymbolMinMaxA0.0600.075A10.0500.065B10.0220.028D0.2800.305D1.150 BSCD2.075 BSCD3-0.305E0.3450.365E10.200 BSCE20.100 BSCE3-0.365e0.050 BSCh0.040 REFj0.020 REFL0.0450.055L10.0450.055L20.0750.125ND4NE5Document # SRAM104 REV BRECTANGULAR LEADLESS CHIP CARRIER

RECTANGULAR LEADLESS CHIP CARRIER (SMALL)

Page 8 of 10

Pkg #P1# Pins18 (300 Mil)SymbolMinMaxA-0.210A10.015-b0.0140.022b20.0450.070C0.0080.014D0.8800.920E10.2400.280E0.3000.325e0.100 BSCeB-0.430L0.1150.150α0°15°Document # SRAM104 REV BPLASTIC DUAL IN-LINE PACKAGE

P4C148/P4C149

Page 9 of 10

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P4C148/P4C149

REVISIONS

DOCUMENT NUMBER:DOCUMENT TITLE:REV.ORAB

ISSUEDATE1997Oct-05Apr-07

SRAM104

P4C148/P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS

ORIG. OFCHANGEDABJDBJDB

DESCRIPTION OF CHANGENew Data SheetChange logo to PyramidAdded 45 and 55 ns speeds

Document # SRAM104 REV BPage 10 of 10