LPC2368资料

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LPC23/66/68

Single-chip 16-bit/32-bit microcontrollers; up to 512 kB ﬂashwith ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC

Rev. 02 — 1 October 2007

Preliminary data sheet

1.General description

TheLPC23/66/68microcontrollersarebasedona16-bit/32-bitARM7TDMI-SCPUwithreal-time emulation that combines the microcontroller with up to 512kB of embeddedhigh-speed ﬂash memory. A 128-bit wide memory interface and a unique acceleratorarchitecture enable 32-bit code execution at the maximum clock rate. For critical

performanceininterruptserviceroutinesandDSPalgorithms,thisincreasesperformanceup to 30% over Thumb mode. For critical code size applications, the alternative 16-bitThumb mode reduces code by more than 30% with minimal performance penalty.The LPC23/66/68 are ideal for multi-purpose serial communication applications. Theyincorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed devicewith 4kB of endpoint RAM, four UARTs, two CAN channels, an SPI interface, two

Synchronous Serial Ports (SSP), three I2C interfaces, and an I2S interface. This blend ofserial communications interfaces combined with an on-chip 4MHz internal oscillator,SRAM of up to 32 kB, 16kB SRAM for Ethernet, 8kB SRAM for USB and generalpurpose use, together with 2kB battery powered SRAM make these devices very wellsuited for communication gateways and protocol converters. Various 32-bit timers, animproved 10-bit ADC, 10-bit DAC, one PWM unit, a CAN control unit, and up to 70 fastGPIO lines with up to 12 edge or level sensitive external interrupt pins make thesemicrocontrollers particularly suitable for industrial control and medical systems.

2.Features

IARM7TDMI-S processor, running at up to 72MHz.

IUp to 512kB on-chip ﬂash program memory with In-System Programming (ISP) andIn-Application Programming (IAP) capabilities. Flash program memory is on the ARMlocal bus for high performance CPU access.

I8/32kB of SRAM on the ARM local bus for high performance CPU access.

I16kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.I8kB SRAM for general purpose DMA use also accessible by the USB.

IDual Advanced High-performance Bus (AHB) system that provides for simultaneousEthernet DMA, USB DMA, and program execution from on-chip ﬂash with no

contention between those functions. A bus bridge allows the Ethernet DMA to accessthe other AHB subsystem.

IAdvanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.IGeneralPurposeAHBDMAcontroller(GPDMA)thatcanbeusedwiththeSSPserialinterfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port,as well as for memory-to-memory transfers.

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ISerial interfaces:

NEthernet MAC with associated DMA controller. These functions reside on anindependent AHB bus.

NUSB 2.0 full-speed device with on-chip PHY and associated DMA controller.

NFourUARTswithfractionalbaudrategeneration,onewithmodemcontrolI/O,onewith IrDA support, all with FIFO.NCAN controller with two channels.NSPI controller.

NTwoSSPcontrollers,withFIFOandmulti-protocolcapabilities.OneisanalternatefortheSPIport,sharingitsinterruptandpins.ThesecanbeusedwiththeGPDMAcontroller.

NThree I2C-bus interfaces (one with open-drain and two with standard port pins).NI2S (Inter-IC Sound) interface for digital audio input or output. It can be used withthe GPDMA.

IOther peripherals:

NSD/MMC memory card interface (LPC2368 only).

N70 general purpose I/O pins with conﬁgurable pull-up/down resistors.N10-bit ADC with input multiplexing among 6 pins.N10-bit DAC.

NFour general purpose timers/counters with a total of 8 capture inputs and 10compare outputs. Each timer block has an external count input.

NOne PWM/timer block with support for three-phase motor control. The PWM hastwo external count inputs.

NReal-Time Clock (RTC) with separate power pin, clock source can be the RTCoscillator or the APB clock.

N2kBSRAMpoweredfromtheRTCpowerpin,allowingdatatobestoredwhentherest of the chip is powered off.

NWatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,the RTC oscillator, or the APB clock.

IStandard ARM test/debug interface for compatibility with existing tools.IEmulation trace module supports real-time trace.ISingle 3.3V power supply (3.0V to 3.6V).

IFour reduced power modes: idle, sleep, power-down, and deep power-down.

IFour external interrupt inputs conﬁgurable as edge/level sensitive. All pins on PORT0and PORT2 can be used as edge sensitive interrupt sources.

IProcessor wake-up from Power-down mode via any interrupt able to operate duringPower-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernetwake-up interrupt).

ITwo independent power domains allow ﬁne tuning of power consumption based onneeded features.

IEach peripheral has its own clock divider for further power saving.

IBrownout detect with separate thresholds for interrupt and forced reset.IOn-chip power-on reset.

IOn-chip crystal oscillator with an operating range of 1MHz to 24MHz.

I4MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used asthe system clock. When used as the CPU clock, does not allow CAN and USB to run.

LPC23_66_68_2

Preliminary data sheetRev. 02 — 1 October 20072 of 47

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Fast communication chip

IOn-chip PLL allows CPU operation up to the maximum CPU rate without the need fora high frequency crystal. May be run from the main oscillator, the internal RCoscillator, or the RTC oscillator.

IVersatile pin function selections allow more possibilities for using on-chip peripheralfunctions.

3.Applications

IIII

Industrial controlMedical systemsProtocol converterCommunications

4.Ordering information

Table 1.

Ordering information

PackageNameLPC23FBD100LPC2366FBD100LPC2368FBD100

LQFP100Descriptionplastic low proﬁle quad ﬂat package; 100 leads; body 14× 14× 1.4 mmVersionSOT407-1Type number4.1Ordering options

Table 2.

Ordering options

Flash(kB)Localbus8EtherUSBSD/GPChannelsTempdeviceMMCDMACANADCDACrangeEthernetGP/RTCTotalnet+4kBbuffersUSBFIFO168234RMIIyesnoyes261−40°Cto

+85°C−40°Cto

+85°C

SRAM (kB)Type numberLPC23FBD100128LPC2366FBD10025632168258RMIIyesnoyes261

LPC2368FBD10051232168258RMIIyesyesyes261

Preliminary data sheetRev. 02 — 1 October 20073 of 47

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5.Block diagram

XTAL1XTAL2VDDATMSTDItrace signalsTRSTTCKTDOEXTIN0RESETVDD(3V3)VREFVSSA, VSSVDD(DCDC)(3V3)LPC23/66/68P0, P1, P2,P3, P4HIGH-SPEEDGPI/O70 PINSTOTAL8/32 kBSRAMTEST/DEBUGINTERFACEEMULATIONTRACE MODULE128/256/512 kBFLASHPLLsystemclockSYSTEMFUNCTIONSINTERNAL RCOSCILLATORINTERNALCONTROLLERSSRAMFLASHARM7TDMI-SVECTOREDINTERRUPTCONTROLLERAHBBRIDGE8 kBSRAMAHB1AHB2AHBBRIDGERMII(8)ETHERNETMAC WITHDMA16 kBSRAMMASTERAHB TOSLAVEPORTAPB BRIDGEPORTAHB TOAPB BRIDGEUSB WITH4 kB RAM AND DMAVBUSUSB_D+, USB_D−USB_CONNECTUSB_UP_LEDGP DMACONTROLLERI2SRX_CLKI2STX_CLKI2SRX_WSI2STX_WSI2SRX_SDAI2STX_SDASCK, SCK0MOSI, MOSI0MISO, MISO0SSEL, SSEL1SCK1MOSI1MIS01SSEL1MCICLK, MCIPWRMCICMD,MCIDAT[3:0]TXD0, TXD2, TXD3RXD0, RXD2, RXD3TXD1RXD1DTR1, RTS1DSR1, CTS1, DCD1,RI1CAN1, CAN2I2C0, I2C1, I2C2RD1, RD2TD1, TD2SCL0, SCL1, SCL2SDA0, SDA1, SDA2EINT3 to EINT0P0, P22 × CAP0/CAP1/CAP2/CAP34 × MAT2,2 × MAT0/MAT1/MAT36 × PWM12 × PCAP1P0, P1EXTERNAL INTERRUPTSCAPTURE/COMPARETIMER0/TIMER1/TIMER2/TIMER3I2S INTERFACEPWM1SPI, SSP0 INTERFACELEGACY GPI/O52 PINS TOTALA/D CONVERTERSSP1 INTERFACE6 × AD0SD/MMC CARDINTERFACE(1)UART0, UART2, UART3AOUTVBATpower domain 2power domain 2RTCX1RTCX2D/A CONVERTER2 kB BATTERY RAMREAL-TIMECLOCKRTCOSCILLATORUART1WATCHDOG TIMERSYSTEM CONTROL002aac566(1)LPC2368 only.Fig 1.LPC23/66/68 block diagramLPC23_66_68_2

Preliminary data sheetRev. 02 — 1 October 20074 of 47

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6.Pinning information

6.1Pinning

1007675512650002aac5761LPC23FBD100LPC2366FBD100LPC2368FBD10025Fig 2.LPC23/66/68 pinning6.2Pin description

Table 3.SymbolP0[0] to P0[31]Pin description

PinTypeI/ODescriptionPort 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Theoperation of port 0 pins depends upon the pin function selected via the Pin Connectblock. Pins 12, 13, 14, and 31 of this port are not available.P0[0] —General purpose digital input/output pin.RD1 —CAN1 receiver input.

TXD3 —Transmitter output for UART3.

SDA1 —I2C1 data input/output (this is not an open-drain pin).P0[1] —General purpose digital input/output pin.TD1 —CAN1 transmitter output.RXD3 —Receiver input for UART3.

SCL1 —I2C1 clock input/output (this is not an open-drain pin).P0[2] —General purpose digital input/output pin.TXD0 —Transmitter output for UART0.

P0[3] —General purpose digital input/output pin.RXD0 —Receiver input for UART0.

P0[4] —General purpose digital input/output pin.

I2SRX_CLK —Receive Clock. It is driven by the master and received by the slave.Corresponds to the signal SCK in theI2S-bus speciﬁcation.RD2 —CAN2 receiver input.

CAP2[0] —Capture input for Timer2, channel 0.

P0[0]/RD1/TXD3/46[1]SDA1

I/OIOI/O

P0[1]/TD1/RXD3/47[1]SCL1

I/OOII/O

P0[2]/TXD0P0[3]/RXD0P0[4]/

I2SRX_CLK/RD2/CAP2[0]

98[1]99[1]81[1]

I/OOI/OII/OI/OII

Preliminary data sheetRev. 02 — 1 October 20075 of 47

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Table 3.SymbolPin description …continuedPin80[1]TypeI/OI/OOI

DescriptionP0[5] —General purpose digital input/output pin.I2SRX_WS —Receive Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in theI2S-bus speciﬁcation.TD2 —CAN2 transmitter output.

CAP2[1] —Capture input for Timer2, channel 1.P0[6] —General purpose digital input/output pin.

I2SRX_SDA —Receive data. It is driven by the transmitter and read by the receiver.Corresponds to the signal SD in theI2S-bus speciﬁcation.SSEL1 —Slave Select for SSP1.

MAT2[0] —Match output for Timer2, channel 0.P0[7] —General purpose digital input/output pin.

I2STX_CLK —Transmit Clock. It is driven by the master and received by the slave.Corresponds to the signal SCK in theI2S-bus speciﬁcation.SCK1 —Serial Clock for SSP1.

MAT2[1] —Match output for Timer2, channel 1.P0[8] —General purpose digital input/output pin.

I2STX_WS —Transmit Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in theI2S-bus speciﬁcation.MISO1 —Master In Slave Out for SSP1.MAT2[2] —Match output for Timer2, channel 2.P0[9] —General purpose digital input/output pin.

I2STX_SDA —Transmit data. It is driven by the transmitter and read by the receiver.Corresponds to the signal SD in theI2S-bus speciﬁcation.MOSI1 —Master Out Slave In for SSP1.MAT2[3] —Match output for Timer2, channel 3.P0[10] —General purpose digital input/output pin.TXD2 —Transmitter output for UART2.

SDA2 —I2C2 data input/output (this is not an open-drain pin).MAT3[0] —Match output for Timer3, channel 0.P0[11] —General purpose digital input/output pin.RXD2 —Receiver input for UART2.

SCL2 —I2C2 clock input/output (this is not an open-drain pin).MAT3[1] —Match output for Timer3, channel 1.P0[15] —General purpose digital input/output pin.TXD1 —Transmitter output for UART1.SCK0 —Serial clock for SSP0.SCK —Serial clock for SPI.

P0[16] —General purpose digital input/output pin.RXD1 —Receiver input for UART1.SSEL0 —Slave Select for SSP0.SSEL —Slave Select for SPI.

P0[5]/I2SRX_WS/TD2/CAP2[1]

P0[6]/

I2SRX_SDA/SSEL1/MAT2[0]

79[1]I/OI/OI/OO

P0[7]/

I2STX_CLK/SCK1/MAT2[1]

78[1]I/OI/OI/OO

P0[8]/

I2STX_WS/MISO1/MAT2[2]

77[1]I/OI/OI/OO

P0[9]/

I2STX_SDA/MOSI1/MAT2[3]

76[1]I/OI/OI/OO

P0[10]/TXD2/SDA2/MAT3[0]

48[1]I/OOI/OO

P0[11]/RXD2/SCL2/MAT3[1]

49[1]I/OII/OO

P0[15]/TXD1/SCK0/SCK

62[1]I/OOI/OI/O

P0[16]/RXD1/SSEL0/SSEL

63[1]I/OII/OI/O

Preliminary data sheetRev. 02 — 1 October 20076 of 47

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Table 3.SymbolPin description …continuedPin61[1]TypeI/OII/OI/O

DescriptionP0[17] —General purpose digital input/output pin.CTS1 —Clear to Send input for UART1.MISO0 —Master In Slave Out for SS1MISO —Master In Slave Out for SPI.

P0[18] —General purpose digital input/output pin.DCD1 —Data Carrier Detect input for UART1.MOSI0 —Master Out Slave In for SSP0.MOSI —Master Out Slave In for SPI.

P0[19] —General purpose digital input/output pin.DSR1 —Data Set Ready input for UART1.

MCICLK —Clock output line for SD/MMC interface. (LPC2368 only)SDA1 —I2C1 data input/output (this is not an open-drain pin).P0[20] —General purpose digital input/output pin.DTR1 —Data Terminal Ready output for UART1.

MCICMD —Command line for SD/MMC interface. (LPC2368 only)SCL1 —I2C1 clock input/output (this is not an open-drain pin).P0[21] —General purpose digital input/output pin.RI1 —Ring Indicator input for UART1.

MCIPWR —Power Supply Enable for external SD/MMC power supply. (LPC2368only)

RD1 —CAN1 receiver input.

P0[22] —General purpose digital input/output pin.RTS1 —Request to Send output for UART1.

MCIDAT0 —Data line for SD/MMC interface. (LPC2368 only)TD1 —CAN1 transmitter output.

P0[23] —General purpose digital input/output pin.AD0[0] —A/D converter 0, input 0.

I2SRX_CLK —Receive Clock. It is driven by the master and received by the slave.Corresponds to the signal SCK in theI2S-bus speciﬁcation.CAP3[0] —Capture input for Timer3, channel 0.P0[24] —General purpose digital input/output pin.AD0[1] —A/D converter 0, input 1.

I2SRX_WS —Receive Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in theI2S-bus speciﬁcation.CAP3[1] —Capture input for Timer3, channel 1.P0[25] —General purpose digital input/output pin.AD0[2] —A/D converter 0, input 2.

I2SRX_SDA —Receive data. It is driven by the transmitter and read by the receiver.Corresponds to the signal SD in theI2S-bus speciﬁcation.TXD3 —Transmitter output for UART3.

P0[17]/CTS1/MISO0/MISO

P0[18]/DCD1/MOSI0/MOSI

60[1]I/OII/OI/O

P0[19]/DSR1/MCICLK/SDA1

59[1]I/OIOI/O

P0[20]/DTR1/MCICMD/SCL1

58[1]I/OOII/O

P0[21]/RI1/MCIPWR/RD1

57[1]I/OIOI

P0[22]/RTS1/MCIDAT0/TD1

56[1]I/OOOO

P0[23]/AD0[0]/I2SRX_CLK/CAP3[0]

9[2]I/OII/OI

P0[24]/AD0[1]/I2SRX_WS/CAP3[1]

8[2]I/OII/OI

P0[25]/AD0[2]/I2SRX_SDA/TXD3

7[2]I/OII/OO

Preliminary data sheetRev. 02 — 1 October 20077 of 47

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Table 3.SymbolPin description …continuedPin6[3]TypeI/OIOI

DescriptionP0[26] —General purpose digital input/output pin.AD0[3] —A/D converter 0, input 3.AOUT —D/A converter output.RXD3 —Receiver input for UART3.

P0[27] —General purpose digital input/output pin.

SDA0 —I2C0 data input/output. Open-drain output (for I2C-bus compliance).P0[28] —General purpose digital input/output pin.

SCL0 —I2C0 clock input/output. Open-drain output (for I2C-bus compliance).P0[29] —General purpose digital input/output pin.USB_D+ —USB bidirectional D+ line.

P0[30] —General purpose digital input/output pin.USB_D− —USB bidirectional D− line.

Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. Theoperation of port 1 pins depends upon the pin function selected via the Pin Connectblock. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available.P1[0] —General purpose digital input/output pin.ENET_TXD0 —Ethernet transmit data 0.P1[1] —General purpose digital input/output pin.ENET_TXD1 —Ethernet transmit data 1.P1[4] —General purpose digital input/output pin.ENET_TX_EN —Ethernet transmit data enable.P1[8] —General purpose digital input/output pin.ENET_CRS —Ethernet carrier sense.

P1[9] —General purpose digital input/output pin.ENET_RXD0 —Ethernet receive data.

P1[10] —General purpose digital input/output pin.ENET_RXD1 —Ethernet receive data.

P1[14] —General purpose digital input/output pin.ENET_RX_ER —Ethernet receive error.

P1[15] —General purpose digital input/output pin.

ENET_REF_CLK/ENET_RX_CLK —Ethernet receiver clock.P1[16] —General purpose digital input/output pin.ENET_MDC —Ethernet MIIM clock.

P1[17] —General purpose digital input/output pin.ENET_MDIO —Ethernet MI data input and output.P1[18] —General purpose digital input/output pin.

USB_UP_LED —USB GoodLink LED indicator. It is LOW when device is conﬁgured(non-control endpoints enabled). It is HIGH when the device is not conﬁgured orduring global suspend.

PWM1[1] —Pulse Width Modulator 1, channel 1 output.CAP1[0] —Capture input for Timer1, channel 0.

P0[26]/AD0[3]/AOUT/RXD3

P0[27]/SDA0P0[28]/SCL0P0[29]/USB_D+P0[30]/USB_D−P1[0] to P1[31]

25[4]24[4]29[5]30[5]

I/OI/OI/OI/OI/OI/OI/OI/OI/O

P1[0]/

ENET_TXD0P1[1]/

ENET_TXD1P1[4]/

ENET_TX_ENP1[8]/

ENET_CRSP1[9]/

ENET_RXD0P1[10]/

ENET_RXD1P1[14]/

ENET_RX_ER

95[1]94[1]93[1]92[1]91[1]90[1][1]

I/OOI/OOI/OOI/OII/OII/OII/OII/OII/OII/OI/OI/OO

P1[15]/88[1]ENET_REF_CLKP1[16]/

ENET_MDCP1[17]/

ENET_MDIOP1[18]/

USB_UP_LED/PWM1[1]/CAP1[0]

87[1]86[1]32[1]

Preliminary data sheetRev. 02 — 1 October 20078 of 47

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Table 3.SymbolPin description …continuedPin33[1]34[1]

TypeI/OII/OOI/O

35[1]

I/OOI/O

36[1]37[1]

I/OOI/OOI/O

38[1]

I/OOI/O

39[1]40[1]

I/OOI/OOI

43[1]44[1]

I/OII/OIO

45[1]

I/OIO

21[2]

I/OII

DescriptionP1[19] —General purpose digital input/output pin.CAP1[1] —Capture input for Timer1, channel 1.P1[20] —General purpose digital input/output pin.PWM1[2] —Pulse Width Modulator 1, channel 2 output.SCK0 —Serial clock for SSP0.

P1[21] —General purpose digital input/output pin.PWM1[3] —Pulse Width Modulator 1, channel 3 output.SSEL0 —Slave Select for SSP0.

P1[22] —General purpose digital input/output pin.MAT1[0] —Match output for Timer1, channel 0.P1[23] —General purpose digital input/output pin.PWM1[4] —Pulse Width Modulator 1, channel 4 output.MISO0 —Master In Slave Out for SSP0.

P1[24] —General purpose digital input/output pin.PWM1[5] —Pulse Width Modulator 1, channel 5 output.MOSI0 —Master Out Slave in for SSP0.

P1[25] —General purpose digital input/output pin.MAT1[1] —Match output for Timer1, channel 1.P1[26] —General purpose digital input/output pin.PWM1[6] —Pulse Width Modulator 1, channel 6 output.CAP0[0] —Capture input for Timer0, channel 0.P1[27] —General purpose digital input/output pin.CAP0[1] —Capture input for Timer0, channel 1.P1[28] —General purpose digital input/output pin.PCAP1[0] —Capture input for PWM1, channel 0.MAT0[0] —Match output for Timer0, channel 0.P1[29] —General purpose digital input/output pin.PCAP1[1] —Capture input for PWM1, channel 1.MAT0[1] —Match output for Timer0, channel 0.P1[30] —General purpose digital input/output pin.VBUS —Indicates the presence of USB bus power.Note: This signal must be HIGH for USB reset to occur.AD0[4] —A/D converter 0, input 4.

P1[31] —General purpose digital input/output pin.SCK1 —Serial Clock for SSP1.AD0[5] —A/D converter 0, input 5.

Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. Theoperation of port 2 pins depends upon the pin function selected via the Pin Connectblock. Pins 14 through 31 of this port are not available.

P1[19]/CAP1[1]P1[20]/PWM1[2]/SCK0

P1[21]/PWM1[3]/SSEL0

P1[22]/MAT1[0]P1[23]/PWM1[4]/MISO0

P1[24]/PWM1[5]/MOSI0

P1[25]/MAT1[1]P1[26]/PWM1[6]/CAP0[0]

P1[27]/CAP0[1]P1[28]/PCAP1[0]/MAT0[0]P1[29]/PCAP1[1]/MAT0[1]P1[30]/VBUS/AD0[4]

P1[31]/SCK1/AD0[5]

20[2]I/OI/OII/O

P2[0] to P2[31]

Preliminary data sheetRev. 02 — 1 October 20079 of 47

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Table 3.SymbolPin description …continuedPin75[1]TypeI/OOOO

74[1]

I/OOIO

73[1]

I/OOIO

70[1]

I/OOIO

69[1]

I/OOIO

68[1]

I/OOOO

67[1]

I/OIIO

66[1]

I/OIOO

65[1]

I/OOOOI/OOII

DescriptionP2[0] —General purpose digital input/output pin.PWM1[1] —Pulse Width Modulator 1, channel 1 output.TXD1 —Transmitter output for UART1.TRACECLK —Trace Clock.

P2[1] —General purpose digital input/output pin.PWM1[2] —Pulse Width Modulator 1, channel 2 output.RXD1 —Receiver input for UART1.PIPESTAT0 —Pipeline Status, bit 0.

P2[2] —General purpose digital input/output pin.PWM1[3] —Pulse Width Modulator 1, channel 3 output.CTS1 —Clear to Send input for UART1.PIPESTAT1 —Pipeline Status, bit 1.

P2[3] —General purpose digital input/output pin.PWM1[4] —Pulse Width Modulator 1, channel 4 output.DCD1 —Data Carrier Detect input for UART1.PIPESTAT2 —Pipeline Status, bit 2.

P2[4] —General purpose digital input/output pin.PWM1[5] —Pulse Width Modulator 1, channel 5 output.DSR1 —Data Set Ready input for UART1.TRACESYNC —Trace Synchronization.P2[5] —General purpose digital input/output pin.PWM1[6] —Pulse Width Modulator 1, channel 6 output.DTR1 —Data Terminal Ready output for UART1.TRACEPKT0 —Trace Packet, bit 0.

P2[6] —General purpose digital input/output pin.PCAP1[0] —Capture input for PWM1, channel 0.RI1 —Ring Indicator input for UART1.TRACEPKT1 —Trace Packet, bit 1.

P2[7] —General purpose digital input/output pin.RD2 —CAN2 receiver input.

RTS1 —Request to Send output for UART1.TRACEPKT2 —Trace Packet, bit 2.

P2[8] —General purpose digital input/output pin.TD2 —CAN2 transmitter output.TXD2 —Transmitter output for UART2.TRACEPKT3 —Trace Packet, bit 3.

P2[9] —General purpose digital input/output pin.

USB_CONNECT —Signal used to switch an external 1.5 kΩ resistor under softwarecontrol. Used with the SoftConnect USB feature.RXD2 —Receiver input for UART2.EXTIN0 —External Trigger Input.

P2[0]/PWM1[1]/TXD1/

TRACECLK

P2[1]/PWM1[2]/RXD1/

PIPESTAT0

P2[2]/PWM1[3]/CTS1/

PIPESTAT1

P2[3]/PWM1[4]/DCD1/

PIPESTAT2

P2[4]/PWM1[5]/DSR1/

TRACESYNC

P2[5]/PWM1[6]/DTR1/

TRACEPKT0

P2[6]/PCAP1[0]/RI1/

TRACEPKT1

P2[7]/RD2/RTS1/

TRACEPKT2

P2[8]/TD2/TXD2/

TRACEPKT3

[1]P2[9]/

USB_CONNECT/RXD2/EXTIN0

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Table 3.SymbolPin description …continuedPin53[6]TypeI/ODescriptionP2[10] —General purpose digital input/output pin.Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take overcontrol of the part after a reset.

IEINT0 —External interrupt 0 input.P2[11] —General purpose digital input/output pin.EINT1 —External interrupt 1 input.MCIDAT1 —Data line for SD/MMC interface. (LPC2368 only)

I2STX_CLK —Transmit Clock. It is driven by the master and received by the slave.Corresponds to the signal SCK in theI2S-bus speciﬁcation.P2[12] —General purpose digital input/output pin.EINT2 —External interrupt 2 input.MCIDAT2 —Data line for SD/MMC interface. (LPC2368 only)

I2STX_WS —Transmit Word Select. It is driven by the master and received by theslave. Corresponds to the signal WS in theI2S-bus speciﬁcation.P2[13] —General purpose digital input/output pin.EINT3 —External interrupt 3 input.MCIDAT3 —Data line for SD/MMC interface. (LPC2368 only)

I2STX_SDA —Transmit data. It is driven by the transmitter and read by the receiver.Corresponds to the signal SD in theI2S-bus speciﬁcation.

Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. Theoperation of port 3 pins depends upon the pin function selected via the Pin Connectblock. Pins 0 through 24, and 27 through 31 of this port are not available.P3[25] —General purpose digital input/output pin.MAT0[0] —Match output for Timer0, channel 0.PWM1[2] —Pulse Width Modulator 1, output 2.P3[26] —General purpose digital input/output pin.MAT0[1] —Match output for Timer0, channel 1.PWM1[3] —Pulse Width Modulator 1, output 3.

Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. Theoperation of port 4 pins depends upon the pin function selected via the Pin Connectblock. Pins 0 through 27, 30, and 31 of this port are not available.P4[28] —General purpose digital input/output pin.MAT2[0] —Match output for Timer2, channel 0.TXD3 —Transmitter output for UART3.

P4[29] —General purpose digital input/output pin.MAT2[1] —Match output for Timer2, channel 1.RXD3 —Receiver input for UART3.TDO —Test Data out for JTAG interface.TDI —Test Data in for JTAG interface.TMS —Test Mode Select for JTAG interface.TRST —Test Reset for JTAG interface.TCK —Test Clock for JTAG interface.

P2[10]/EINT0P2[11]/EINT1/MCIDAT1/I2STX_CLK

52[6]I/OIOI/O

P2[12]/EINT2/MCIDAT2/I2STX_WS

51[6]I/OIOI/O

P2[13]/EINT3/MCIDAT3/I2STX_SDA

50[6]I/OIOI/O

P3[0] to P3[31]I/O

P3[25]/MAT0[0]/PWM1[2]

27[1]I/OOO

P3[26]/MAT0[1]/PWM1[3]

26[1]I/OOOI/O

P4[0] to P4[31]

P4[28]/MAT2[0]/TXD3

82[1]I/OOO

P4[29]/MAT2[1]/RXD3

85[1]I/OOI

TDOTDITMSTRSTTCK

1[1]2[1]3[1]4[1]5[1]

OIIII

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Table 3.SymbolRTCKPin description …continuedPin100[1]TypeI/ODescriptionRTCK —JTAG interface control signal.Note:LOWonthispinwhileRESETisLOWenablesETMpins(P2[9:0])tooperateasTrace port after reset.

RSTOUTRESET14[1]17[7]OIRSTOUT —This is a 1.8V pin. LOW on this pin indicates LPC23/66/68 being inReset state.

external reset input: A LOW on this pin resets the device, causing I/O ports andperipherals to take on their default states, and processor execution to begin ataddress 0. TTL with hysteresis, 5V tolerant.

Input to the oscillator circuit and internal clock generator circuits.Output from the oscillator ampliﬁer.Input to the RTC oscillator circuit.Output from the RTC oscillator circuit.ground: 0V reference.

XTAL1XTAL2RTCX1RTCX2VSS

22[8]23[8]16[8]18[8]15, 31,41, 55,72, 97,83[9]11[10]28, 54,71,96[11]13, 42,84[12]10[13]

IOIOI

VSSAVDD(3V3)

analog ground: 0V reference. This should nominally be the same voltage as VSS,but should be isolated to minimize noise and error.

3.3V supply voltage: This is the power supply voltage for the I/O ports.

VDD(DCDC)(3V3)VDDA

3.3VDC-to-DCconvertersupplyvoltage:Thisisthesupplyvoltagefortheon-chipDC-to-DC converter only.

analog 3.3V pad supply voltage: This should be nominally the same voltage asVDD(3V3) but should be isolated to minimize noise and error. This voltage is used topower the ADC and DAC.

ADCreference:ThisshouldbenominallythesamevoltageasVDD(3V3)butshouldbeisolated to minimize noise and error. Level on this pin is used as a reference for ADCand DAC.

RTC power supply: 3.3V on this pin supplies the power to the RTC.

VREF12[13]I

VBAT

[1][2][3][4][5][6][7][8][9]

19[13]I

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When conﬁgured as a DAC input,digital section of the pad is disabled.

5V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When conﬁgured as the DAC output,digital section of the pad is disabled.

Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz speciﬁcation compatible pad. It requires an external pull-up to provide outputfunctionality. When power is switched off, this pin connected to the I2C-bus is ﬂoating and does not disturb the I2C lines.Pad provides digital I/O and USB functions. It is designed in accordance with theUSB speciﬁcation, revision 2.0 (Full-speed andLow-speed mode only).

5 V tolerant pad with 5ns glitch ﬁlter providing digital I/O functions with TTL levels and hysteresis5 V tolerant pad with 20ns glitch ﬁlter providing digital I/O function with TTL levels and hysteresisPad provides special analog functionality.Pad provides special analog functionality.

[10]Pad provides special analog functionality.[11]Pad provides special analog functionality.[12]Pad provides special analog functionality.[13]Pad provides special analog functionality.

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7.Functional description

7.1Architectural overview

The LPC23/66/68 microcontroller consists of an ARM7TDMI-S CPU with emulationsupport, the ARM7 local bus for closely coupled, high-speed access to the majority ofon-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals, and theAMBA APB for connection to other on-chip peripheral functions. The microcontrollerpermanently conﬁgures the ARM7TDMI-S processor for little-endian byte order.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16kB SRAM. In addition, a bus bridge is provided that allows the secondaryAHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space intooff-chip memory or unused space in memory residing on AHB1.

Insummary,busmasterswithaccesstoAHB1aretheARM7itself,theGPDMAfunction,andtheEthernetblock(viathebusbridgefromAHB2).BusmasterswithaccesstoAHB2are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2MB range of addresses at the very top of the 4GBARM memory space. Each AHB peripheral is allocated a 16kB address space within theAHB address space. Lower speed peripheral functions are connected to the APB bus.TheAHBtoAPBbridgeinterfacestheAPBbustotheAHBbus.APBperipheralsarealsoallocated a 2MB range of addresses, beginning at the 3.5GB address point. Each APBperipheral is allocated a 16kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offershigh performance and very low power consumption. The ARM architecture is based onReduced Instruction Set Computer (RISC) principles, and the instruction set and relateddecode mechanism are much simpler than those of microprogrammed complex

instruction set computers. This simplicity results in a high instruction throughput andimpressive real-time interrupt response from a small and cost-effective processor core.Pipelinetechniquesareemployedsothatallpartsoftheprocessingandmemorysystemscan operate continuously. Typically, while one instruction is being executed, its successoris being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known asThumb, which makes it ideally suited to high-volume applications with memoryrestrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, theARM7TDMI-S processor has two instruction sets:

•The standard 32-bit ARM set•A 16-bit Thumb set

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The Thumb set’s 16-bit instruction length allows it to approach twice the density ofstandard ARM code while retaining most of the ARM’s performance advantage over atraditional 16-bit processor using 16-bit registers. This is possible because Thumb codeoperates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65% of the code size of ARM, and 160% of theperformance of an equivalent ARM processor connected to a 16-bit memory system.

7.2On-chip ﬂash programming memory

The LPC23/66/68 incorporate a 128kB, 256kB, and 512kB ﬂash memory systemrespectively. This memory may be used for both code and data storage. Programming ofthe ﬂash memory may be accomplished in several ways. It may be programmed InSystem via the serial port (UART0). The application program may also erase and/or

program the ﬂash while the application is running, allowing a great degree of ﬂexibility fordata storage ﬁeld and ﬁrmware upgrades.

The ﬂash memory is 128bits wide and includes pre-fetching and buffering techniques toallow it to operate at SRAM speeds of 72MHz.

The LPC23/66/68 provides a minimum of 100000 write/erase cycles and 20 years ofdata retention.

7.3On-chip SRAM

The LPC23/66/68 includes a SRAM memory of 8kB, 32kB, and 32kB respectively,reserved for the ARM processor exclusive use. This RAM may be used for code and/ordata storage and may be accessed as 8bits, 16bits, and 32bits.

A 16kB SRAM block serving as a buffer for the Ethernet controller and an 8kB SRAMassociated with the USB device can be used both for data and code storage, too.

RemainingSRAMsuchasa4kBUSBFIFOanda2kBRTCSRAMcanbeusedfordatastorageonly.TheRTCSRAMisbatterypoweredandretainsthecontentintheabsenceofthe main power supply.

7.4Memory map

The LPC23/66/68 memory map incorporates several distinct regions as shown inFigure3.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in eitherﬂash memory (default), boot ROM, or SRAM (seeSection7.25.6).

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4.0 GBAHB PERIPHERALS3.75 GBAPB PERIPHERALS3.5 GB0xFFFF FFFF0xF000 00000xE000 00003.0 GBRESERVED ADDRESS SPACE0xC000 00002.0 GBBOOT ROM AND BOOT FLASH(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)RESERVED ADDRESS SPACEETHERNET RAM (16 kB)USB RAM (8 KB)RESERVED ADDRESS SPACE0x8000 00000x7FE0 3FFF0x7FE0 00000x7FD0 1FFF0x7FD0 00000x4000 80000x4000 7FFF32 kB LOCAL ON-CHIP STATIC RAM (LPC2366/LPC2368)0x4000 20000x4000 1FFF0x4000 00008 kB LOCAL ON-CHIP STATIC RAM (LPC23)1.0 GBRESERVED FOR ON-CHIP MEMORY0x0008 00000x0007 FFFF0x0004 00000x0003 FFFF0x0002 00000x0001 FFFF0x0000 0000TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2368)TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2366)0.0 GBTOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC23)002aac577Fig 3.LPC23/66/68 memory map7.5Interrupt controller

TheARMprocessorcorehastwointerruptinputscalledInterruptRequest(IRQ)andFastInterrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can beprogrammed as FIQ or vectored IRQ types. The programmable assignment schememeans that priorities of interrupts from the various peripherals can be dynamicallyassigned and adjusted.

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FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORsthe requests to produce the FIQ signal to the ARM processor. The fastest possible FIQlatency is achieved when only one request is classiﬁed as FIQ, because then the FIQservice routine can simply start dealing with that device. But if more than one request isassigned to the FIQ class, the FIQ service routine can read a word from the VIC thatidentiﬁes which FIQ source(s) is (are) requesting an interrupt.

VectoredIRQs,whichincludeallinterruptrequeststhatarenotclassiﬁedasFIQs,haveaprogrammable interrupt priority. When more than one interrupt is assigned the same

priorityandoccursimultaneously,theoneconnectedtothelowestnumberedVICchannelwill be serviced ﬁrst.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to theARMprocessor.TheIRQserviceroutinecanstartbyreadingaregisterfromtheVICandjumping to the address supplied by that register.

7.5.1Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have severalinterrupt ﬂags. Individual interrupt ﬂags may also represent more than one interruptsource.

Any pin on PORT0 and PORT2 (total of 42 pins) regardless of the selected function, canbe programmed to generate an interrupt on a rising edge, a falling edge, or both. Suchinterrupt request coming from PORT0 and/or PORT2 will be combined with the EINT3interrupt requests.

7.6Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than onefunction. Conﬁguration registers control the multiplexers to allow connection between thepin and the on chip peripherals.

Peripheralsshouldbeconnectedtotheappropriatepinspriortobeingactivatedandpriortoanyrelatedinterrupt(s)beingenabled.Activityofanyenabledperipheralfunctionthatisnot mapped to a related pin should be considered undeﬁned.

7.7General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC23/66/68peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA streamprovides unidirectional serial DMA transfers for a single source and destination. Forexample, a bidirectional port requires one stream for transmit and one for receive. Thesource and destination areas can each be either a memory region or a peripheral, andcan be accessed through the AHB master.

7.7.1Features

•Two DMA channels. Each channel can support a unidirectional transfer.

•The GPDMA can transfer data between the 8kB SRAM and peripherals such as the

SD/MMC, two SSP, and I2S interfaces.

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•Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMAburst size is set by programming the GPDMA.

•Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

•Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

•Hardware DMA channel priority. Each DMA channel has a speciﬁc hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. Ifrequests from two channels become active at the same time the channel with thehighest priority is serviced ﬁrst.

•AHBslaveDMAprogramminginterface.TheGPDMAisprogrammedbywritingtothe

DMA control registers over the AHB slave interface.

•One AHB bus master for transferring data. This interface transfers data when a DMA

request goes active.

•32-bit AHB master bus width.

•Incrementing or non-incrementing addressing for source and destination.

•Programmable DMA burst size. The DMA burst size can be programmed to more

efﬁcientlytransferdata.UsuallytheburstsizeissettohalfthesizeoftheFIFOintheperipheral.

•Internal four-word FIFO per channel.

•Supports 8-bit, 16-bit, and 32-bit wide transactions.

•AninterrupttotheprocessorcanbegeneratedonaDMAcompletionorwhenaDMA

error has occurred.

•Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

masked.

•Rawinterruptstatus.TheDMAerrorandDMAcountrawinterruptstatuscanberead

prior to masking.

7.8Fast general purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by theGPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registersallowsettingorclearinganynumberofoutputssimultaneously.Thevalueoftheoutput register may be read back as well as the current state of the port pins.LPC23/66/68 use accelerated GPIO functions:

•GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved.

•Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

•All GPIO registers are byte and half-word addressable.•Entire port value can be written in one instruction.

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Additionally, any pin on PORT0 and PORT2 (total of 42 pins) providing a digital functioncanbeprogrammedtogenerateaninterruptonarisingedge,afallingedge,orboth.Theedge detection is asynchronous, so it may operate when clocks are not present such asduring Power-down mode. Each enabled interrupt can be used to wake up the chip fromPower-down mode.

7.8.1Features

•Bitlevelsetandclearregistersallowasingleinstructiontosetorclearanynumberof

bits in one port.

•Direction control of individual bits.•All I/O default to inputs after reset.

•Backward compatibility with other earlier devices is maintained with legacy PORT0

and PORT1 registers appearing at the original addresses on the APB bus.

7.9Ethernet

The Ethernet block contains a full featured 10Mbit/s or 100Mbit/s Ethernet MACdesigned to provide optimized performance through the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplexoperation, ﬂow control, control frames, hardware acceleration for transmit retry, receivepacketﬁlteringandwake-uponLANactivity.Automaticframetransmissionandreceptionwith scatter-gather DMA off-loads many operations from the CPU.

TheEthernetblockandtheCPUshareadedicatedAHBsubsystemthatisusedtoaccesstheEthernetSRAMforEthernetdata,control,andstatusinformation.AllotherAHBtrafﬁcin the LPC23/66/68 takes place on a different AHB subsystem, effectively separatingEthernetactivityfromtherestofthesystem.TheEthernetDMAcanalsoaccesstheUSBSRAM if it is not being used by the USB block.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serialbus.

7.9.1Features

•Ethernet standards support:

–Supports 10Mbit/s or 100Mbit/s PHY devices including 10Base-T, 100Base-TX,100Base-FX, and 100Base-T4.–Fully compliant with IEEE standard 802.3.

–Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex backpressure.–Flexible transmit and receive frame options.–Virtual Local Area Network (VLAN) frame support.

•Memory management:

–Independent transmit and receive buffers memory mapped to shared SRAM.–DMA managers with scatter/gather DMA and arrays of frame descriptors.–Memory trafﬁc optimized by buffering and pre-fetching.

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•Enhanced Ethernet features:

–Receive ﬁltering.

–Multicast and broadcast frame support for both transmit and receive.–Optional automatic Frame Check Sequence (FCS) insertion with CircularRedundancy Check (CRC) for transmit.–Selectable automatic transmit frame padding.

–Over-length frame support for both transmit and receive allows any length frames.–Promiscuous receive mode.

–Automatic collision back-off and frame retransmission.–Includes power management by clock switching.

–Wake-on-LAN power management support allows system wake-up: using thereceive ﬁlters or a magic frame detection ﬁlter.

•Physical interface:

–Attachment of external PHY chip through standard RMII interface.–PHY register access is available via the MIIM interface.

7.10USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between ahost and a number (127 maximum) of peripherals. The host controller allocates the USBbandwidth to attached devices through a token based protocol. The bus supports hotplugging, unplugging, and dynamic conﬁguration of the devices. All transactions areinitiated by the host controller.

7.10.1USB device controller

The device controller enables 12Mbit/s data exchange with a USB host controller. Itconsists of register interface, serial interface engine, endpoint buffer memory, and theDMAcontroller.TheserialinterfaceenginedecodestheUSBdatastreamandwritesdatato the appropriate end point buffer memory. The status of a completed USB transfer orerror condition is indicated via status registers. An interrupt is also generated if enabled.The DMA controller when enabled transfers data between the endpoint buffer and theUSB RAM.

7.10.2Features

•••••

Fully compliant withUSB 2.0 speciﬁcation (full speed).

Supports 32 physical (16 logical) endpoints with a 4kB USB buffer.Supports Control, Bulk, Interrupt and Isochronous endpoints.Scalable realization of endpoints at run time.

Endpoint Maximum packet size selection (up to USB maximum speciﬁcation) bysoftware at run time.

•Supports SoftConnect and GoodLink features.

•While USB is in the Suspend mode, LPC23/66/68 can enter one of the reduced

Power-down modes and wake up on a USB activity.

•Supports DMA transfers with the DMA RAM of 8kB on all non-control endpoints.

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•Allows dynamic switching between CPU-controlled and DMA modes.•Double buffer implementation for Bulk and Isochronous endpoints.

7.11CAN controller and acceptance ﬁlters

The Controller Area Network (CAN) is a serial communications protocol which efﬁcientlysupports distributed real-time control with a very high level of security. Its domain ofapplication ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing thedevice to be used as a gateway, switch, or router among a number of CAN buses inindustrial or automotive applications.

EachCANcontrollerhasaregisterstructuresimilartotheNXPSJA1000andthePeliCANLibraryblock,butthe8-bitregistersofthosedeviceshavebeencombinedin32-bitwordstoallowsimultaneousaccessintheARMenvironment.Themainoperationaldifferenceisthat the recognition of received Identiﬁers, known in CAN terminology as AcceptanceFiltering, has been removed from the CAN controllers and centralized in a globalAcceptance Filter.

7.11.1Features

•••••

Two CAN controllers and buses.Data rates to 1Mbit/s on each bus.32-bit register and RAM access.

Compatible withCAN speciﬁcation 2.0B, ISO 118-1.

Global Acceptance Filter recognizes 11-bit and 29-bit receive identiﬁers for all CANbuses.

Standard Identiﬁers.

•Acceptance Filter can provide FullCAN-style automatic reception for selected•Full CAN messages can generate interrupts.

7.1210-bit ADC

TheLPC23/66/68containoneADC.Itisasingle10-bitsuccessiveapproximationADCwith six channels.

7.12.1Features

••••••••

10-bit successive approximation ADC.Input multiplexing among 6 pins.Power-down mode.

Measurement range 0 V to Vi(VREF).10-bit conversion time≥ 2.44µs.

Burst conversion mode for single or multiple inputs.

Optional conversion on transition of input pin or Timer Match signal.

Individual result registers for each ADC channel to reduce interrupt overhead.

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7.1310-bit DAC

The DAC allows the LPC23/66/68 to generate a variable analog output. The maximumoutput value of the DAC is Vi(VREF).

7.13.1Features

•••••

10-bit DAC

Resistor string architectureBuffered outputPower-down modeSelectable output drive

7.14UARTs

The LPC23/66/68 each contain four UARTs. In addition to standard transmit andreceive data lines, UART1 also provides a full modem control handshake interface.TheUARTsincludeafractionalbaudrategenerator.Standardbaudratessuchas115200can be achieved with any crystal frequency above 2MHz.

7.14.1Features

••••

16B Receive and Transmit FIFOs.

Built-in fractional baud rate generator covering wide range of baud rates without aneed for external crystals of particular values.

mechanism that enables software ﬂow control implementation.

•Fractional divider for baud rate control, auto baud capabilities and FIFO control•UART1 equipped with standard modem interface signals. This module also provides

full support for hardware ﬂow control (auto-CTS/RTS).

•UART3 includes an IrDA mode to support infrared communication.

7.15SPI serial I/O controller

The LPC23/66/68 each contain one SPI controller. SPI is a full duplex serial interfacedesigned to handle multiple masters and slaves connected to a given bus. Only a singlemaster and a single slave can communicate on the interface during a given data transfer.During a data transfer the master always sends 8bits to 16bits of data to the slave, andthe slave always sends 8bits to 16bits of data to the master.

7.15.1Features

•••••

LPC23_66_68_2

Compliant with SPI speciﬁcation

Synchronous, serial, full duplex communicationCombined SPI master and slave

Maximum data bit rate of one eighth of the input clock rate8bits to 16bits per transfer

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7.16SSP serial I/O controller

The LPC23/66/68 each contain two SSP controllers. The SSP controller is capable ofoperationonaSPI,4-wireSSI,orMicrowirebus.Itcaninteractwithmultiplemastersandslaves on the bus. Only a single master and a single slave can communicate on the busduring a given data transfer. The SSP supports full duplex transfers, with frames of 4bitsto16bitsofdataﬂowingfromthemastertotheslaveandfromtheslavetothemaster.Inpractice, often only one of these data ﬂows carries meaningful data.

7.16.1Features

•Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire

buses

•••••

Synchronous serial communicationMaster or slave operation

8-frame FIFOs for both transmit and receive4-bit to 16-bit frame

DMA transfers supported by GPDMA

7.17SD/MMC card interface (LPC2368 only)

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SDmemory cards. The SD card interface conforms to theSD Multimedia Card SpeciﬁcationVersion 2.11.

7.17.1Features

•TheMCIinterfaceprovidesallfunctionsspeciﬁctotheSD/MMCmemorycard.These

includetheclockgenerationunit,powermanagementcontrol,andcommandanddatatransfer.

•Conforms toMultimedia Card Speciﬁcation v2.11.

•Conforms toSecure Digital Memory Card Physical Layer Speciﬁcation, v0.96.•Canbeusedasamultimediacardbusorasecuredigitalmemorycardbushost.The

SD/MMC can be connected to several multimedia cards or a single secure digitalmemory card.

•DMA supported through the GPDMA controller.

7.18I2C-bus serial I/O controllers

The LPC23/66/68 each contain three I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line(SCL), and a serial data line (SDA). Each device is recognized by a unique address andcanoperateaseitherareceiver-onlydevice(e.g.,anLCDdriver)oratransmitterwiththecapability to both receive and send information (such as memory). Transmitters and/orreceiverscanoperateineithermasterorslavemode,dependingonwhetherthechiphasto initiate a data transfer or is only addressed. The I2C is a multi-master bus, it can becontrolled by more than one bus master connected to it.

The I2C-bus implemented in LPC23/66/68 supports bit rates up to 400kbit/s (FastI2C-bus).

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7.18.1Features

•I2C0 is a standard I2C compliant bus interface with open-drain pins.

•I2C1 and I2C2 use standard I/O pins and do not support powering off of individual

devices connected to the same bus lines.

•••••

Easy to conﬁgure as master, slave, or master/slave.Programmable clocks allow versatile rate control.Bidirectional data transfer between masters and slaves.Multi-master bus (no central master).

Arbitration between simultaneously transmitting masters without corruption of serialdata on the bus.one serial bus.

•Serialclocksynchronizationallowsdeviceswithdifferentbitratestocommunicatevia•Serialclocksynchronizationcanbeusedasahandshakemechanismtosuspendand

resume serial transfer.

•The I2C-bus can be used for test and diagnostic purposes.

7.19I2S-bus serial I/O controllers

The I2S-bus provides a standard communication interface for digital audio applications.TheI2S-bus speciﬁcation deﬁnes a 3-wire serial bus using one data line, one clock line,andonewordselectsignal.ThebasicI2Sconnectionhasonemaster,whichisalwaysthemaster, and one slave. The I2S interface on the LPC23/66/68 provides a separatetransmit and receive channel, each of which can operate as either a master or a slave.

7.19.1Features

•Theinterfacehasseparateinput/outputchannelseachofwhichcanoperateinmaster

or slave mode.

•Capable of handling 8-bit, 16-bit, and 32-bit word sizes.•Mono and stereo audio data supported.

•The sampling frequency can range from 16kHz to 48kHz (16, 22.05, 32, 44.1,

48)kHz.

••••

Conﬁgurable word select period in master mode (separately for I2S input and output).Two 8-word FIFO data buffers are provided, one for transmit and one for receive.Generates interrupt requests when buffer levels cross a programmable boundary.TwoDMArequests,controlledbyprogrammablebufferlevels.Theseareconnectedtothe GPDMA block.

•Controls include reset, stop and mute options separately for I2S input and I2S output.

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7.20General purpose 32-bit timers/external event counters

TheLPC23/66/68includefour32-bitTimer/Counters.TheTimer/Counterisdesignedtocount cycles of the system derived clock or an externally-supplied clock. It can optionallygenerate interrupts or perform other actions at speciﬁed timer values, based on fourmatch registers. The Timer/Counter also includes two capture inputs to trap the timervalue when an input signal transitions, optionally generating an interrupt.

7.20.1Features

•A 32-bit Timer/Counter with a programmable 32-bit prescaler.•Counter or Timer operation.

•Two 32-bit capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

•Four 32-bit match registers that allow:

–Continuous operation with optional interrupt generation on match.–Stop timer on match with optional interrupt generation.–Reset timer on match with optional interrupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.–Set HIGH on match.–Toggle on match.–Do nothing on match.

7.21Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, althoughonly the PWM function is pinned out on the LPC23/66/68. The Timer is designed tocountcyclesofthesystemderivedclockandoptionallyswitchpins,generateinterruptsorperformotheractionswhenspeciﬁedtimervaluesoccur,basedonsevenmatchregisters.The PWM function is in addition to these features, and is based on match register events.The ability to separately control rising and falling edge locations allows the PWM to beusedformoreapplications.Forinstance,multi-phasemotorcontroltypicallyrequiresthreenon-overlapping PWM outputs with individual control of all three pulse widths andpositions.

Two match registers can be used to provide a single edge controlled PWM output. Onematch register (PWMMR0) controls the PWM cycle rate, by resetting the count uponmatch. The other match register controls the PWM edge position. Additional single edgecontrolled PWM outputs require only one match register each, since the repetition rate isthesameforallPWMoutputs.MultiplesingleedgecontrolledPWMoutputswillallhavearising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.Three match registers can be used to provide a PWM output with both edges controlled.Again, the PWMMR0 match register controls the PWM cycle rate. The other matchregisters control the two PWM edge positions. Additional double edge controlled PWMoutputs require only two match registers each, since the repetition rate is the same for allPWM outputs.

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With double edge controlled PWM outputs, speciﬁc match registers control the rising andfalling edge of the output. This allows both positive going PWM pulses (when the risingedge occurs prior to the falling edge), and negative going PWM pulses (when the fallingedge occurs prior to the rising edge).

7.21.1Features

•LPC23/66/68 has one PWM block with Counter or Timer operation (may use the

peripheral clock or one of the capture inputs as the clock source).

•Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:–Continuous operation with optional interrupt generation on match.–Stop timer on match with optional interrupt generation.–Reset timer on match with optional interrupt generation.

•Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go high at the beginning of each cycle unless theoutput is a constant low. Double edge controlled PWM outputs can have either edgeoccur at any position within a cycle. This allows for both positive going and negativegoing pulses.

•Pulse period and width can be any number of timer counts. This allows complete

ﬂexibility in the trade-off between resolution and repetition rate. All PWM outputs willoccur at the same repetition rate.

•Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

•Match register updates are synchronized with pulse outputs to prevent generation of

erroneouspulses.Softwaremust‘release’newmatchvaluesbeforetheycanbecomeeffective.

•May be used as a standard timer if the PWM mode is not enabled.•A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

7.22Watchdog timer

Thepurposeofthewatchdogistoresetthemicrocontrollerwithinareasonableamountoftime if it enters an erroneous state. When enabled, the watchdog will generate a systemreset if the user program fails to ‘feed’ (or reload) the watchdog within a predeterminedamount of time.

7.22.1Features

•Internally resets chip if not periodically reloaded.•Debug mode.

•Enabledbysoftwarebutrequiresahardwareresetorawatchdogreset/interrupttobe

disabled.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.•Flag to indicate watchdog reset.

•Programmable 32-bit timer with internal prescaler.

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•Selectable time period from (Tcy(WDCLK)×256×4) to (Tcy(WDCLK)×232×4) in

multiples of Tcy(WDCLK)×4.

•The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the

Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range ofpotential timing choices of Watchdog operation under different power reduction

conditions. It also provides the ability to run the WDT from an entirely internal sourcethat is not dependent on an external crystal and its associated components andwiring, for increased reliability.

7.23RTC and battery RAM

TheRTCisasetofcountersformeasuringtimewhensystempowerison,andoptionallywhen it is off. It uses little power in Power-down mode. On the LPC23/66/68, the RTCcan be clocked by a separate 32.768kHz oscillator, or by a programmable prescaledivider based on the APB clock. Also, the RTC is powered by its own power supply pin,VBAT,whichcanbeconnectedtoabatteryortothesame3.3Vsupplyusedbytherestofthe device.

TheVBATpinsuppliespoweronlytotheRTCandtheBatteryRAM.Thesetwofunctionsrequire a minimum of power to operate, which can be supplied by an external battery.

7.23.1Features

•Measures the passage of time to maintain a calendar and clock.•Ultra low power design to support battery powered systems.

•ProvidesSeconds,Minutes,Hours,DayofMonth,Month,Year,DayofWeek,andDay

of Year.

•Dedicated 32kHz oscillator or programmable prescaler from APB clock.

•Dedicated power supply pin can be connected to a battery or to the main 3.3V.

•Periodicinterruptscanbegeneratedfromincrementsofanyﬁeldofthetimeregisters,

and selected fractional second values.

•2kB data SRAM powered by VBAT.

•RTC and Battery RAM power supply is isolated from the rest of the chip.

7.24Clocking and power control

7.24.1Crystal oscillators

The LPC23/66/68 includes three independent oscillators. These are the Main

Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be usedfor more than one purpose as required in a particular application. Any of the three clocksources can be chosen by software to drive the PLL and ultimately the CPU.

Following reset, the LPC23/66/68 will operate from the Internal RC oscillator until

switchedbysoftware.Thisallowssystemstooperatewithoutanyexternalcrystalandthebootloader code to operate at a known frequency.

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7.24.1.1Internal RC oscillator

TheIRCmaybeusedastheclocksourcefortheWDT,and/orastheclockthatdrivesthePLL and subsequently the CPU. The nominal IRC frequency is 4MHz. The IRC istrimmed to 1% accuracy.

Upon power-up or any chip reset, the LPC23/66/68 uses the IRC as the clock source.Software may later switch to one of the other available clock sources.

7.24.1.2Main oscillator

ThemainoscillatorcanbeusedastheclocksourcefortheCPU,withorwithoutusingthePLL.Themainoscillatoroperatesatfrequenciesof1MHzto24MHz.Thisfrequencycanbe boosted to a higher frequency, up to the maximum CPU operating frequency, by thePLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clockfrequency is referred to as CCLK elsewhere in this document. The frequencies of

PLLCLKIN and CCLK are the same value unless the PLL is active and connected. Theclock frequency for each peripheral can be selected individually and is referred to asPCLK. Refer toSection7.24.2 for additional information.

7.24.1.3RTC oscillator

TheRTCoscillatorcanbeusedastheclocksourcefortheRTCand/ortheWDT.Also,theRTC oscillator can be used to drive the PLL and the CPU.

7.24.2PLL

The PLL accepts an input clock frequency in the range of 32kHz to 50MHz. The inputfrequency is multiplied up to a high frequency, then divided down to provide the actualclock used by the CPU and the USB block.

ThePLLinput,intherangeof32kHZto50MHz,mayinitiallybedivideddownbyavalue‘N’, which may be in the range of 1 to 256. This input division provides a wide range ofoutput frequencies from the same input frequency.

Following the PLL input divider is the PLL multiplier. This can multiply the input divideroutput through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in therange of 1 through 32768. The resulting frequency must be in the range of 275MHz to550MHz.ThemultiplierworksbydividingtheCCOoutputbythevalueofM,thenusingaphase-frequency detector to compare the divided CCO output to the multiplier input. Theerror value is used to adjust the CCO frequency.

The PLL is turned off and bypassed following a chip Reset and by entering Power-downmode.PLLisenabledbysoftwareonly.TheprogrammustconﬁgureandactivatethePLL,wait for the PLL to Lock, then connect to the PLL as a clock source.

7.24.3Wake-up timer

TheLPC23/66/68beginsoperationatpower-upandwhenawakenedfromPower-downmode or Deep power-down mode by using the 4MHz IRC oscillator as the clock source.Thisallowschipoperationtoresumequickly.IfthemainoscillatororthePLLisneededbythe application, software will need to enable these features and wait for them to stabilizebefore they are used as a clock source.

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Whenthemainoscillatorisinitiallyactivated,thewake-uptimerallowssoftwaretoensurethat the main oscillator is fully functional before the processor uses it as a clock sourceand starts to execute instructions. This is important at power on, all types of Reset, andwhenever any of the aforementioned functions are turned off for any reason. Since theoscillatorandotherfunctionsareturnedoffduringPower-downmode,anywake-upoftheprocessor from Power-down mode makes use of the wake-up Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begincode execution. When power is applied to the chip, or when some event caused the chipto exit Power-down mode, some time is required for the oscillator to produce a signal ofsufﬁcientamplitudetodrivetheclocklogic.Theamountoftimedependsonmanyfactors,including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and itselectricalcharacteristics(ifaquartzcrystalisused),aswellasanyotherexternalcircuitry(e.g.,capacitors),andthecharacteristicsoftheoscillatoritselfundertheexistingambientconditions.

7.24.4Power control

The LPC23/66/68 supports a variety of power control features. There are four specialmodes of processor power reduction: Idle mode, Sleep mode, Power-down mode, andDeep power-down mode. The CPU clock rate may also be controlled as needed by

changing clock sources, reconﬁguring PLL values, and/or altering the CPU clock dividervalue. This allows a trade-off of power versus processing speed based on applicationrequirements. In addition, Peripheral Power Control allows shutting down the clocks toindividualon-chipperipherals,allowingﬁnetuningofpowerconsumptionbyeliminatingalldynamicpoweruseinanyperipheralsthatarenotrequiredfortheapplication.Eachoftheperipherals has its own clock divider which provides even better power control.

The LPC23/66/68 also implements a separate power domain in order to allow turningoff power to the bulk of the device while maintaining operation of the RTC and a smallSRAM, referred to as the Battery RAM.

7.24.4.1

Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interruptoccurs. Peripheral functions continue operation during Idle mode and may generateinterrupts to cause the processor to resume execution. Idle mode eliminates dynamicpower used by the processor itself, memory systems and related controllers, and internalbuses.

7.24.4.2

Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. Theprocessor state and registers, peripheral registers, and internal SRAM values arepreserved throughout Sleep mode and the logic levels of chip pins remain static. TheoutputoftheIRCisdisabledbuttheIRCisnotpowereddownforafastwake-uplater.The32kHz RTC oscillator is not stopped because the RTC interrupts may be used as thewake-up source. The PLL is automatically turned off and disconnected. The CCLK andUSB clock dividers automatically get reset to zero.

The Sleep mode can be terminated and normal operation resumed by either a Reset orcertain speciﬁc interrupts that are able to function without clocks. Since all dynamicoperation of the chip is suspended, Sleep mode reduces chip power consumption to averylowvalue.TheﬂashmemoryisleftoninSleepmode,allowingaveryquickwake-up.

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Onthewake-upofSleepmode,iftheIRCwasusedbeforeenteringSleepmode,thecodeexecution and peripherals activities will resume after 4 cycles expire. If the main externaloscillator was used, the code execution will resume when 4096 cycles expire.The customers need to reconﬁgure the PLL and clock dividers accordingly.

7.24.4.3

Power-down mode

Power-down mode does everything that Sleep mode does, but also turns off the IRCoscillator and the ﬂash memory. This saves more power, but requires waiting for

resumptionofﬂashoperationbeforeexecutionofcodeordataaccessintheﬂashmemorycan be accomplished.

On the wake-up of Power-down mode, if the IRC was used before entering Power-downmode, it will take IRC 60µs to start-up. After this 4 IRC cycles will expire before the codeexecutioncanthenberesumedifthecodewasrunningfromSRAM.Inthemeantime,theﬂashwake-uptimerthencounts4MHzIRCclockcyclestomakethe100µsﬂashstart-uptime. When it times out, access to the ﬂash will be allowed. The customers need toreconﬁgure the PLL and clock dividers accordingly.

7.24.4.4

Deep power-down mode

Deeppower-downmodeislikePower-downmode,buttheon-chipregulatorthatsuppliespower to internal logic is also shut off. This produces the lowest possible powerconsumption without actually removing power from the entire chip. Since Deep

power-down mode shuts down the on-chip logic power supply, there is no register ormemory retention, and resumption of operation involves the same activities as a full-chipreset.

If power is supplied to the LPC23/66/68 during Deep power-down mode, wake-up canbe caused by external Reset.

While in Deep power-down mode, external device power may be removed. In this case,the LPC23/66/68 will start up when external power is restored.

Essential data may be retained through Deep power-down mode (or through completepoweringoffofthechip)bystoringdataintheBatteryRAM,aslongastheexternalpowerto the VBAT pin is maintained.

7.24.4.5

Power domains

The LPC23/66/68 provides two independent power domains that allow the bulk of thedevice to have power removed while maintaining operation of the RTC and the BatteryRAM.

The 3.3V (VDD(3V3)) pins power both the on-chip DC-to-DC converter and the I/O pads.These pins provide the power for the CPU and most of the peripherals. If power isremoved from the VDD(3V3) pins, the CPU and related peripherals stop.

TheVBATpinsuppliespoweronlytotheRTCandtheBatteryRAM.Thesetwofunctionsrequire a minimum of power to operate, which can be supplied by an external battery.

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7.25System control

7.25.1Reset

Reset has four sources on the LPC23/66/68: theRESET pin, the Watchdog reset,power-on reset, and the BrownOut Detection (BOD) circuit. TheRESET pin is a Schmitttriggerinputpin.AssertionofchipResetbyanysource,oncetheoperatingvoltageattainsa usable level, starts the Wake-up timer (see description inSection 7.24.3 “Wake-uptimer”), causing reset to remain asserted until the external Reset is de-asserted, theoscillator is running, a ﬁxed number of clocks have passed, and the ﬂash controller hascompleted its initialization.

When the internal Reset is removed, the processor begins executing at address 0, whichisinitiallytheResetvectormappedfromtheBootBlock.Atthatpoint,alloftheprocessorand peripheral registers have been initialized to predetermined values.

7.25.2Brownout detection

TheLPC23/66/68includes2-stagemonitoringofthevoltageontheVDD(3V3)pins.Ifthisvoltage falls below 2.95V, the BOD asserts an interrupt signal to the Vectored InterruptController. This signal can be enabled for interrupt in the Interrupt Enable Register in theVICinordertocauseaCPUinterrupt;ifnot,softwarecanmonitorthesignalbyreadingadedicated status register.

Thesecondstageoflow-voltagedetectionassertsResettoinactivatetheLPC23/66/68whenthevoltageontheVDD(3V3)pinsfallsbelow2.65V.ThisResetpreventsalterationofthe ﬂash as operation of the various elements of the chip would otherwise becomeunreliable due to low voltage. The BOD circuit maintains this reset down below 1V, atwhich point the power-on reset circuitry maintains the overall Reset.

Both the 2.95V and 2.65V thresholds include some hysteresis. In normal operation, thishysteresis allows the 2.95V detection to reliably interrupt, or a regularly executed eventloop to sense the condition.

7.25.3Code security

This feature of the LPC23/66/68 allows an application to control whether it can bedebugged or protected from observation.

If after reset the on-chip bootloader detects a valid checksum in ﬂash and reads

0x87654321 from address 0x1FC in ﬂash, debugging will be disabled and thus the codeinﬂashwillbeprotectedfromobservation.Oncedebuggingisdisabled,itcanbeenabledby performing a full chip erase using the ISP.

7.25.4AHB bus

The LPC23/66/68 implements two AHB buses in order to allow the Ethernet block tooperatewithoutinterferencecausedbyothersystemactivity.TheprimaryAHB,referredtoas AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface,and 8kB SRAM primarily intended for use by the USB.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16kB SRAM. In addition, a bus bridge is provided that allows the secondaryAHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space intounused space in memory residing on AHB1.

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In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, theGPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masterswith access to AHB2 are the ARM7 and the Ethernet block.

7.25.5External interrupt inputs

The LPC23/66/68 include up to 46 edge sensitive interrupt inputs combined with up toto four level sensitive external interrupt inputs as selectable pin functions. The externalinterrupt inputs can optionally be used to wake up the processor from Power-down mode.

7.25.6Memory mapping control

Thememorymappingcontrolaltersthemappingoftheinterruptvectorsthatappearatthebeginning at address 0x0000 0000. Vectors may be mapped to the bottom of the BootROM or the SRAM. This allows code running in different memory spaces to have controlof the interrupts.

7.26Emulation and debugging

TheLPC23/66/68supportemulationanddebuggingviaaJTAGserialport.Atraceportallowstracingprogramexecution.DebuggingandtracefunctionsaremultiplexedonlywithGPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface

peripherals residing on other pins are available during the development and debuggingphase as they are when the application is run in the embedded system itself.

7.26.1EmbeddedICE

The EmbeddedICE logic provides on-chip debug support. The debugging of the targetsystem requires a host computer running the debugger software and an EmbeddedICEprotocol convertor. The EmbeddedICE protocol convertor converts the Remote DebugProtocol commands to the JTAG data needed to access the ARM7TDMI-S core presenton the target system.

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCCallowsaprogramrunningonthetargettocommunicatewiththehostdebuggeroranotherseparate host without stopping the program ﬂow or even entering the debug state. TheDCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-Score. The DCC allows the JTAG port to be used for sending and receiving data withoutaffecting the normal program ﬂow. The DCC data and control registers are mapped in toaddresses in the EmbeddedICE logic.

7.26.2Embedded trace

SincetheLPC23/66/68havesigniﬁcantamountsofon-chipmemories,itisnotpossibleto determine how the processor core is operating simply by observing the external pins.The ETM provides real-time trace capability for deeply embedded processor cores. Itoutputsinformationaboutprocessorexecutiontoatraceport.Asoftwaredebuggerallowsconﬁguration of the ETM using a JTAG interface and displays the trace information thathas been captured.

TheETMisconnecteddirectlytotheARMcoreandnottothemainAMBAsystembus.Itcompresses the trace information and exports it through a narrow trace port. An externalTrace Port Analyzer captures the trace information under software debugger control. Thetrace port can broadcast the Instruction trace information. Instruction trace (or PC trace)showstheﬂowofexecutionoftheprocessorandprovidesalistofalltheinstructionsthat

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were executed. Instruction trace is signiﬁcantly compressed by only broadcasting branchaddressesaswellasasetofstatussignalsthatindicatethepipelinestatusonacyclebycycle basis. Trace information generation can be controlled by selecting the triggerresource. Trigger resources include address comparators, counters and sequencers.Since trace information is compressed the software debugger requires a static image ofthe code being executed. Self-modifying code can not be traced because of thisrestriction.

7.26.3RealMonitor

RealMonitor is a conﬁgurable software module, developed by ARM Inc., which enablesreal-time debug. It is a lightweight debug monitor that runs in the background while usersdebugtheirforegroundapplication.ItcommunicateswiththehostusingtheDCC,whichispresentintheEmbeddedICElogic.TheLPC23/66/68containaspeciﬁcconﬁgurationofRealMonitor software programmed into the on-chip ROM memory.

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8.Limiting values

Table 4.Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]SymbolVDD(3V3)

Parametersupply voltage (3.3 V)Conditionscore and externalrail

Min3.03.0−0.5

for the RTCon ADC relatedpins

5V tolerant I/Opins; only validwhen the VDD(3V3)supply voltage ispresentother I/O pins

IDDISSTstgPtot(pack)

supply currentground currentstorage temperature

total power dissipation (per package)

based on packageheat transfer, notdevice powerconsumptionhuman bodymodel; all pins

[6][2]

Max3.63.6+4.6+4.6+4.6+5.1+6.0

UnitVVVVVVV

VDD(DCDC)(3V3)DC-to-DC converter supply voltage

(3.3V)VDDAVi(VBAT)Vi(VREF)VIAVI

analog 3.3 V pad supply voltageinput voltage on pin VBATinput voltage on pin VREFanalog input voltageinput voltage

−0.5−0.5−0.5−0.5

[2][3]

−0.5--−40-

VDD(3V3) +0.5100100+1251.5

VmAmA°CW

per supply pinper ground pin

[4][4][5]

Vesd

[1]

electrostatic discharge voltage−2000+2000V

The following applies to the Limiting values:

a)This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessivestaticcharge.Nonetheless,itissuggestedthatconventionalprecautionsbetakentoavoidapplyinggreaterthantheratedmaximum.b)Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to VSS unlessotherwise noted.Including voltage on outputs in 3-state mode.Not to exceed 4.6V.

The peak current is limited to 25 times the corresponding maximum current.Dependent on package type.

Human body model: equivalent to discharging a 100pF capacitor through a 1.5kΩ series resistor.

[2][3][4][5][6]

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9.Static characteristics

Table 5.Static characteristics

Tamb=−40°C to +85°C for commercial applications, unless otherwise speciﬁed.SymbolVDD(3V3)VDD(DCDC)(3V3)VDDAVi(VBAT)Vi(VREF)

Parametersupply voltage (3.3 V)DC-to-DC convertersupply voltage (3.3 V)analog3.3Vpadsupplyvoltage

input voltage on pinVBAT

input voltage on pinVREF

LOW-level input currentVI=0V; no pull-upHIGH-levelinputcurrentVI=VDD(3V3); no

pull-downOFF-state outputcurrent

I/O latch-up current

VO=0V; VO=VDD(3V3);no pull-up/down−(0.5VDD(3V3)) < VI <(1.5VDD(3V3));Tj < 125°C

VIVOVIHVILVhysVOHVOLIOHIOLIOHSIOLSIpdIpu

input voltageoutput voltageHIGH-level inputvoltage

LOW-level input voltagehysteresis voltageHIGH-level outputvoltage

LOW-level outputvoltage

HIGH-level outputcurrent

LOW-level outputcurrent

IOH=−4 mAIOL=−4 mA

VOH=VDD(3V3)−0.4VVOL=0.4V

[6][2]

Conditionscore and external railMin3.03.03.02.02.5

Typ[1]3.33.33.33.33.3

Max3.63.63.63.6VDDA

UnitVVVVV

Standard port pins,RESET, RTCKIILIIHIOZIlatch

--------333100

µAµAµAmA

pin conﬁgured to providea digital functionoutput active

[3][4][5]

002.0--VDD(3V3)−0.4-−44--10−150

----0.4------50−500

5.5VDD(3V3)-0.8--0.4--−4550150−850

VVVVVVVmAmAmAmAµAµAµA

[6]

HIGH-level short-circuitVOH=0Voutput currentLOW-level short-circuitoutput currentpull-down currentpull-up current

VOL=VDDAVI=5VVI=0V

VDD(3V3)[7]

[7]

[8]

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Table 5.Static characteristics …continuedTamb=−40°C to +85°C for commercial applications, unless otherwise speciﬁed.SymbolParameterConditionsVDD(DCDC)(3V3)=3.3V;Tamb=25°C; code

MinTyp[1]MaxUnitIDD(DCDC)act(3V3)active mode DC-to-DC

converter supplycurrent (3.3V)

while(1){}executed from ﬂash; noperipherals enabled;PCLK=CCLKCCLK=10MHzCCLK=72MHzall peripherals enabled;PCLK=CCLK/8CCLK=10MHzCCLK=72MHzall peripherals enabled;PCLK=CCLKCCLK=10MHzCCLK=72MHz

---27125150

---mAmAµA

--2192

--mAmA

--1563

--mAmA

IDD(DCDC)pd(3V3)

power-down modeDC-to-DC convertersupply current (3.3V)

VDD(DCDC)(3V3) =3.3V;Tamb=25°C

IDD(DCDC)dpd(3V3)deep power-down

mode DC-to-DCconverter supplycurrent (3.3V)IBATact

active mode batterysupply current

-15-µA

DC-to-DC converter onDC-to-DC converter off

[9][9]

2028

---

µAµAV

I2C-bus pins (P0[27] and P0[28])VIHVILVhysVOLILI

Oscillator pinsVi(XTAL1)Vo(XTAL2)Vi(RTCX1)Vo(RTCX2)

input voltage on pinXTAL1

output voltage on pinXTAL2

input voltage on pinRTCX1

output voltage on pinRTCX2

0000

----1.81.81.81.8

VVVV

HIGH-level inputvoltage

LOW-level input voltagehysteresis voltageLOW-level outputvoltage

input leakage current

IOLS=3 mAVI=VDD(3V3)VI=5V

[6]

0.7VDD(3V3)--------210

0.3VDD(3V3)V

VVµAµA

0.4422

0.5VDD(3V3)-

[10]

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Table 5.Static characteristics …continuedTamb=−40°C to +85°C for commercial applications, unless otherwise speciﬁed.SymbolUSB pinsIOZVBUSVDIVCMVth(rs)se

OFF-state outputcurrent

bus supply voltagedifferential inputsensitivity voltagedifferential commonmode voltage rangesingle-ended receiverswitching thresholdvoltage

LOW-level outputvoltage forlow-/full-speedHIGH-level outputvoltage (driven) forlow-/full-speed

RL of 1.5kΩ to 3.6V|(D+)−(D−)|includes VDI range0V--0.20.80.8

-----±105.25-2.52.0

µAVVVV

ParameterConditionsMinTyp[1]MaxUnitVOL

--0.18V

VOHRL of 15kΩ to GND

2.8-3.5V

CtransZDRV

transceiver capacitancepin to GND

with 33Ω series resistor;driver output

steady state driveimpedance for driver

whichisnothigh-speedcapable

pull-up resistance

SoftConnect=ON

[11]

-36

2044.1

pFΩ

Rpu

[1][2][3][4][5][6][7][8][9]

1.1-1.9kΩ

Typical ratings are not guaranteed. The values listed are at room temperature (25°C), nominal supply voltages.The RTC typically fails when Vi(VBAT) drops below 1.6V.Including voltage on outputs in 3-state mode.VDD(3V3) supply voltages must be present.

3-state outputs go into 3-state mode when VDD(3V3) is grounded.Accounts for 100mV voltage drop in all supply lines.Only allowed for a short time period.

Minimum condition for VI=4.5V, maximum condition for VI=5.5V.On pin VBAT.

[10]To VSS.

[11]Includes external resistors of 18Ω±1% on D+ and D−.

Table 6.ADC static characteristics

VDDA=2.5V to 3.6V; Tamb=−40°C to +85°C unless otherwise speciﬁed; ADC frequency 4.5MHz.SymbolVIACiaEDEL(adj)EO

Parameteranalog input voltageanalog input capacitancedifferential linearity errorintegral non-linearityoffset error

[1][2][3][1][4][1][5]

ConditionsMin0----

Typ-----

MaxVDDA1±1±2±3

UnitVpFLSBLSBLSB

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Table 6.ADC static characteristics …continuedVDDA=2.5V to 3.6V; Tamb=−40°C to +85°C unless otherwise speciﬁed; ADC frequency 4.5MHz.SymbolEGETRvsi

[1][2][3][4][5][6][7][8]

Parametergain errorabsolute error

voltage source interfaceresistance

Conditions[1][6][1][7][8]

Min---

Typ---

Max±0.5±440

Unit%LSBkΩ

Conditions: VSSA=0V, VDDA=3.3V.

The ADC is monotonic, there are no missing codes.

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. SeeFigure4.

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve afterappropriate adjustment of gain and offset errors. SeeFigure4.

The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts theideal curve. SeeFigure4.

The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offseterror, and the straight line which ﬁts the ideal transfer curve. SeeFigure4.

Theabsoluteerror(ET)isthemaximumdifferencebetweenthecenterofthestepsoftheactualtransfercurveofthenon-calibratedADCand the ideal transfer curve. SeeFigure4.SeeFigure5.

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offset errorEO1023gainerrorEG10221021102010191018(2)7codeout6(1)5(5)4(4)3(3)21 LSB(ideal)1offset errorEO234567VIA (LSBideal)1 LSB =VDDA − VSSA1024002aac046101018101910201021102210231024(1)Example of an actual transfer curve.(2)The ideal transfer curve.(3)Differential linearity error (ED).(4)Integral non-linearity (EL(adj)).(5)Center of a step of the actual transfer curve.Fig 4.ADC characteristicsLPC23_66_68_2© NXP B.V. 2007. All rights reserved.

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10.Dynamic characteristics

Table 7.Dynamic characteristics of USB pins (full-speed)

CL = 50 pF; Rpu = 1.5kΩ on D+ to VDD(3V3), unless otherwise speciﬁed.SymboltrtftFRFMVCRStFEOPTtFDEOPtJR1tJR2tEOPR1

Parameterrise timefall time

differential rise and fall timematching

output signal crossover voltagesource SE0 interval of EOPsource jitter for differential transitionto SE0 transition

receiver jitter to next transitionreceiver jitter for paired transitionsEOP width at receiver

10% to 90%must reject asEOP; seeFigure7must accept asEOP; seeFigure7[1]

Conditions10% to 90%10% to 90% tr/tf

Min8.57.7-1.3

Typ---------

Max13.813.71092.0175+5+18.5+9-

Unitnsns%Vnsnsnsnsns

seeFigure7seeFigure7160−2−18.5−940

tEOPR2

EOP width at receiver[1]82--ns[1]Characterized but not implemented as production test. Guaranteed by design.

Table 8.Dynamic characteristics

Tamb=−40°C to +85°C for commercial applications; VDD(3V3) over speciﬁed ranges.[1]SymbolExternal clockfoscTcy(clk)tCHCXtCLCXtCLCHtCHCLtf(o)

[1][2][3]

Parameteroscillator frequencyclock cycle timeclock HIGH timeclock LOW timeclock rise timeclock fall timeoutput fall time

ConditionsMin1040

Tcy(clk)×0.4Tcy(clk)×0.4--

Typ[2]-------

Max25100--55-

UnitMHznsnsnsnsnsns

I2C-bus pins (P0[27] and P0[28])

VIH to VIL

20 + 0.1× Cb[3]

Parameters are valid over operating temperature range unless otherwise speciﬁed.

Typical ratings are not guaranteed. The values listed are at room temperature (25°C), nominal supply voltages.Bus capacitance Cb in pF, from 10 pF to 400 pF.

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10.1Timing

VDD − 0.5 V0.45 V0.2VDD + 0.9 V0.2VDD − 0.1 VtCHCLtCLCXTcy(clk)002aaa907tCHCXtCLCHFig 6.External clock timingtPERIODcrossover pointdifferentialdata linescrossover pointextendedsource EOP width: tFEOPTdifferential data to SEO/EOP skewn × tPERIOD + tFDEOPreceiver EOP width: tEOPR1, tEOPR2002aab561Fig 7.Differential data-to-EOP transition skew and EOP widthLPC23_66_68_2© NXP B.V. 2007. All rights reserved.

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11.Application information

11.1Suggested USB interface solutions

VDD(3V3)USB_UP_LEDUSB_CONNECTLPC23XXsoft-connect switchR11.5 kΩVBUSUSB_D+RS = 33 ΩUSB_D−RS = 33 ΩVSS002aac578USB-BconnectorFig 8.LPC23/66/68 USB interface on a self-powered deviceVDD(3V3)R2LPC23XXUSB_UP_LEDVBUSUSB_D+RS = 33 ΩUSB_D−RS = 33 ΩVSSR11.5 kΩUSB-Bconnector002aac579Fig 9.LPC23/66/68 USB interface on a bus-powered deviceLPC23_66_68_2© NXP B.V. 2007. All rights reserved.

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12.Package outline

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

cyX75765150ZEAeEHEwMbppin 1 index1001eZD25vMABvMB26detail XLθLpAA2(A )3A1bpDHDwM05scale10 mmDIMENSIONS (mm are the original dimensions)UNITmmAmax.1.6A10.150.05A21.451.35A30.25bp0.270.17c0.200.09D(1)14.113.9E(1)14.113.9e0.5HDHEL1Lp0.750.45v0.2w0.08y0.08ZD(1)ZE(1)1.150.851.150.85θ7oo016.2516.2515.7515.75Note1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINEVERSION SOT407-1 REFERENCES IEC136E20 JEDECMS-026 JEITAEUROPEANPROJECTIONISSUE DATE00-02-0103-02-20Fig 10.Package outline SOT407-1 (LQFP100)

LPC23_66_68_2

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13.Abbreviations

Table 9.AcronymADCAHBAMBAAPBBODCANDACDCCDMADSPEOPETMGPIOJTAGMIIPHYPLLPWMRMIISE0SPISSISSPTTLUARTUSB

Abbreviations

DescriptionAnalog-to-Digital ConverterAdvanced High-performance Bus

Advanced Microcontroller Bus ArchitectureAdvanced Peripheral BusBrownOut DetectionController Area NetworkDigital-to-Analog ConverterDebug Communication ChannelDirect Memory AccessDigital Signal ProcessingEnd Of Packet

Embedded Trace MacrocellGeneral Purpose Input/OutputJoint Test Action GroupMedia Independent InterfacePhysical LayerPhase-Locked LoopPulse Width Modulator

Reduced Media Independent InterfaceSingle Ended ZeroSerial Peripheral InterfaceSerial Synchronous InterfaceSynchronous Serial PortTransistor-Transistor Logic

Universal Asynchronous Receiver/TransmitterUniversal Serial Bus

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14.Revision history

Table 10.

Revision history

Release date20071001

Data sheet statusPreliminary data sheetPreliminary data sheetChange notice--SupersedesLPC23_66_68_1-Document IDLPC23_66_68_2Modiﬁcations:LPC23_66_68_1•Figure1,7,8 and9: changed incorrect character font20070103LPC23_66_68_2© NXP B.V. 2007. All rights reserved.

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15.Legal information

15.1Data sheet status

Document status[1][2]Objective [short] data sheetPreliminary [short] data sheetProduct [short] data sheet

[1][2][3]

Product status[3]DevelopmentQualiﬁcationProduction

DeﬁnitionThis document contains data from the objective speciﬁcation for product development.This document contains data from the preliminary speciﬁcation.This document contains the product speciﬁcation.

Please consult the most recently issued document before initiating or completing a design.The term ‘short data sheet’ is explained in section “Deﬁnitions”.

Theproductstatusofdevice(s)describedinthisdocumentmayhavechangedsincethisdocumentwaspublishedandmaydifferincaseofmultipledevices.Thelatestproductstatusinformation is available on the Internet at URLhttp://www.nxp.com.

15.2Deﬁnitions

Draft —The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodiﬁcations or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness of

informationincludedhereinandshallhavenoliabilityfortheconsequencesofuse of such information.

Short data sheet —A short data sheet is an extract from a full data sheetwiththesameproducttypenumber(s)andtitle.Ashortdatasheetisintendedforquickreferenceonlyandshouldnotbereliedupontocontaindetailedandfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesofﬁce. In case of any inconsistency or conﬂict with the short data sheet, thefull data sheet shall prevail.

NXP Semiconductors accepts no liability for inclusion and/or use of NXPSemiconductors products in such equipment or applications and thereforesuch inclusion and/or use is at the customer’s own risk.

Applications —Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespeciﬁed use without further testing or modiﬁcation.

Limiting values —Stress above one or more limiting values (as deﬁned intheAbsoluteMaximumRatingsSystemofIEC60134)maycausepermanentdamagetothedevice.Limitingvaluesarestressratingsonlyandoperationofthe device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.

Terms and conditions of sale —NXP Semiconductors products are soldsubjecttothegeneraltermsandconditionsofcommercialsale,aspublishedathttp://www.nxp.com/proﬁle/terms, including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conﬂict between information in this document and suchterms and conditions, the latter will prevail.

No offer to sell or license —Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant,conveyanceorimplicationofanylicenseunderanycopyrights,patentsor other industrial or intellectual property rights.

15.3Disclaimers

General —Information in this document is believed to be accurate and

reliable.However,NXPSemiconductorsdoesnotgiveanyrepresentationsorwarranties,expressedorimplied,astotheaccuracyorcompletenessofsuchinformation and shall have no liability for the consequences of use of suchinformation.

Right to make changes —NXPSemiconductorsreservestherighttomakechanges to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and withoutnotice.Thisdocumentsupersedesandreplacesallinformationsuppliedpriorto the publication hereof.

Suitability for use —NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or

malfunctionofaNXPSemiconductorsproductcanreasonablybeexpectedtoresult in personal injury, death or severe property or environmental damage.

15.4Trademarks

Notice:Allreferencedbrands,productnames,servicenamesandtrademarksare the property of their respective owners.I2C-bus —logois a trademark of NXP B.V.SoftConnect —is a trademark of NXP B.V.GoodLink —is a trademark of NXP B.V.

16.Contact information

For additional information, please visit:http://www.nxp.com

For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com

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17.Contents

1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Ordering information. . . . . . . . . . . . . . . . . . . . . 34.1Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 35Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 46Pinning information. . . . . . . . . . . . . . . . . . . . . . 56.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 57Functional description . . . . . . . . . . . . . . . . . . 137.1Architectural overview. . . . . . . . . . . . . . . . . . . 137.2On-chip ﬂash programming memory . . . . . . . 147.3On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 147.4Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 147.5Interrupt controller . . . . . . . . . . . . . . . . . . . . . 157.5.1Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 167.6Pin connect block . . . . . . . . . . . . . . . . . . . . . . 167.7General purpose DMA controller . . . . . . . . . . 167.7.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.8Fast general purpose parallel I/O. . . . . . . . . . 177.8.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.9Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.9.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.10USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 197.10.1USB device controller. . . . . . . . . . . . . . . . . . . 197.10.2Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197.11CAN controller and acceptance ﬁlters . . . . . . 207.11.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.1210-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.12.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.1310-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.13.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.14UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.14.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.15SPI serial I/O controller. . . . . . . . . . . . . . . . . . 217.15.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.16SSP serial I/O controller. . . . . . . . . . . . . . . . . 227.16.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227.17SD/MMC card interface (LPC2368 only) . . . . 227.17.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227.18I2C-bus serial I/O controllers. . . . . . . . . . . . . . 227.18.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.19I2S-bus serial I/O controllers. . . . . . . . . . . . . . 237.19.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.20

General purpose 32-bit timers/external

event counters . . . . . . . . . . . . . . . . . . . . . . . . 24

7.20.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

LPC23/66/68

Fast communication chip

7.21Pulse width modulator . . . . . . . . . . . . . . . . . .

7.21.1Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257.22Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 257.22.1Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257.23RTC and battery RAM . . . . . . . . . . . . . . . . . . 267.23.1Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267.24Clocking and power control . . . . . . . . . . . . . . 267.24.1Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 267.24.1.1Internal RC oscillator . . . . . . . . . . . . . . . . . . . 277.24.1.2Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 277.24.1.3RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 277.24.2PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277.24.3Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 277.24.4Power control. . . . . . . . . . . . . . . . . . . . . . . . . 287.24.4.1Idle mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 287.24.4.2Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 287.24.4.3Power-down mode . . . . . . . . . . . . . . . . . . . . . 297.24.4.4Deep power-down mode . . . . . . . . . . . . . . . . 297.24.4.5Power domains. . . . . . . . . . . . . . . . . . . . . . . . 297.25System control. . . . . . . . . . . . . . . . . . . . . . . . 307.25.1Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307.25.2Brownout detection . . . . . . . . . . . . . . . . . . . . 307.25.3Code security . . . . . . . . . . . . . . . . . . . . . . . . 307.25.4AHB bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307.25.5External interrupt inputs. . . . . . . . . . . . . . . . . 317.25.6Memory mapping control . . . . . . . . . . . . . . . . 317.26Emulation and debugging. . . . . . . . . . . . . . . . 317.26.1EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 317.26.2Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 317.26.3RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 328Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 339Static characteristics . . . . . . . . . . . . . . . . . . . 3410Dynamic characteristics. . . . . . . . . . . . . . . . . 4010.1Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4111Application information . . . . . . . . . . . . . . . . . 4211.1Suggested USB interface solutions . . . . . . . . 4212Package outline. . . . . . . . . . . . . . . . . . . . . . . . 4313Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 4414Revision history . . . . . . . . . . . . . . . . . . . . . . . 4515Legal information . . . . . . . . . . . . . . . . . . . . . . 4615.1Data sheet status. . . . . . . . . . . . . . . . . . . . . . 4615.2Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4615.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 4615.4Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 4616Contact information . . . . . . . . . . . . . . . . . . . . 4617Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pleasebeawarethatimportantnoticesconcerningthisdocumentandtheproduct(s)described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 1 October 2007

Document identifier: LPC23_66_68_2

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