AEAS-7500资料

AEAS - 7500

Ultra-Precision 16 bit Gray Code Absolute Encoder Module

Data Sheet

Description

The encoder IC consists of 13 signal photo diode channels and 1 monitor photo diode channel and is used for the optical reading of rotary or linear code carriers (i.e. discs or scales). The photodiodes are accompanied with precision amplifiers plus additional circuitry.

The monitor channel is used to drive a constant current source for the highly collimated IR illumination system.

Functional DescriptionBackground

The 13 signal channels are set up as:

1. Two precision defining signals (A0, A09), which are two

90° electrical shifted sine, cosine signals. These signals

are conditioned to be compensated for offset and gain

errors. After conditioning they are on-chip interpolated and computed to a combined absolute 16 bit Gray code,

together with signal channels A1-A11.2. 11 analog (A1-A11) channels, which are directly digitized

by precision comparators with hysteresis tracking. The digitized signals are called D1-D11.3. An internal correction and synchronization module allows the composition of a true 16 bit gray code by

merging the data bits of (1) and (2) by still keeping the

code monotonic. 4. There is a Gray code correction feature for this encoder. This Gray code correction can be disabled/enabled by

the pin KORR.

5. The gain and offset conditioning value of the sine and

cosine signals are preloaded on-chip by factory. This will minimize mechanical sensor misalignment error.

Features

• Two Sine/Cosine true differential outputs with 1024 periods for unit alignment• Integrated highly collimated illumination system

• 11 digital tracks plus 2 sin/cos tracks generate precise

16 bit Gray code

• Ultra fast, 1µs cycle for serial data output word equals

16MHz• The 12 bits MSB is functionable up to 12000 RPM, 16

bit up to 1000RPM• MSB can be inverted for changing the counting direc-tion

• Monitor track for tracking the light level of the LED• Watch dog with alarm output pin LERR

• -25 °C to + 85 °C operating temperatureBenefits

• No battery or capacitor required for position detection during power failure

• Immediate position detection on power upApplications

• Rotary application up to 16 bits / 360° absolute position• Cost effective solution for direct integration into OEM systems• Linear positioning system

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Signal-channels A1-A11

The photocurrent of the photodiodes is fed into a tran-simpedance amplifier. The analog output of the amplifier has a voltage swing of(dark/light) about 1.3V. Every output is transformed by precision comparators into digital signals (D1-D11). The threshold is at VDD/2(=Analog-reference), LSB gray code Correction (Pin KORR)

This function block synchronizes the switching points for the 11 bit gray code of the digital signals D1 to D11 with D0 and D09 (digitized signal of A0 and A09).

The accuracy of the complete 12 bit gray is defined by regulated by the monitor channel.

Monitor Channel with LED Control at pins LEDR and LERR

The analog output signal of the monitor channel is regu-lated by the LED current. An external bipolar transistor(to be connected by user) sets this level to VDD/2 (control voltage at pin LEDR). Thus the signal swing of each output is symmetrical to VDD/2(=Analog-reference)

The error bit at pin LERR is triggered if the Ve of the internal bipolar transistor is larger than VDD/2

Signals Channels A0, A09 with signal conditioning and cali-bration

These two channels give out a sine and cosine wave, which are 90 degree phase shifted. These signals have amplitudes, which are almost constant due to the LED current monitor-ing. Due to amplifier mismatch and mechanical misalign-ment the signals have gain and offset errors. These errors are eliminated by an adaptive signal conditioning circuitry. The conditioning values are on-chip preprogrammed by factory. The analog output signals of A0 and A09 are sup-plied as true-differential voltage with a peak to peak value of 2.0V at the pins A09P, A09N, A0P, A0N.

Interpolator for Channels A0,A09

The interpolator generates the digital signals D0,D09 and

D-1 to D-4. The interpolated signals D-1 to D-4 extend

the 12 bit Gray code of the signals D11….D0 to form a 16

bit Gray code.

D0 and D09 are digitized from A0 and A09. The channels A0-A11 and A09 have very high dynamic bandwidth, which allows a real time monotone 12Bit Gray code at 12000 RPM.

The interpolated 16 bit Gray code can be used up to 1000RPM only. At more than 1000RPM, only the 12 bit Gray code from the MSB side can be used.

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the precision of the signals D0/D09. As these two signals are generated by the gain and offset conditioned analog signals A0 and A09, they are very precise.

This Gray code correction only works for the full 12 bit (4096 steps per revolution).

The correction is not for the 4 excess interpolated bits of the 16 bit Gray code. Gray code correction can be switched on or off by putting the pin KORR =1(on) or =0(off).

MSBINV and DOUT pins

The serial interface consists of a shift register. The most significant bit, MSB(D11) will always be sent first to DOUT. The MSB can be inverted (change code direction) by using pin MSBINV.

DIN and NSL pins

The Serial input DIN allows the configuration as ring reg-ister for multiple transmissions or for cascading 2 or more encoders. DIN is the input of the shift register that shifts the data to DOUT.

The NSL pin controls the shift register, to switch it between load (1) or shift(0) mode. Under load mode, DOUT will give the logic of the MSB, i.e. D11.

Under shift mode (0), coupled with the SCL, the register will be clocked, and gives out the serial word output bit by bit.

As the clock frequency can be up to 16 MHz, the transmis-sion of the full 16 bit word can be done within 1 µs.

Valid data of DOUT should be read when the SCL clock is low. Please refer to timing diagram Figure 4.

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Package Dimensions

CLRadial +Tangential+Z +Z −Notes:

1. 3rd Angle Projection

2. Dimensions are in millimeters

3. Unless specified otherwise, the tolerances are: XX. – ±0.5; XX.X – ±0.2; XX.XX – ±0.034. Note: Codewheel and readhead mounting tolerances for radial, tangential and Z gap are: Radial : ± 50 um Tangential : ± 40um Z Gap : ± 50umFigure 1. Package Dimensions

Device Selection Guide 1

Part Number

AEAS-7500-1GSG0

Resolution

16 bit

Operating

Temperature (°C)

-25 to 85

Output

SSI + 1024 Sine/Cosine Incremental

Output Code

Gray Code

DC Supply Voltage (V)

+4.5 to +5.5

Notes:

1. For other options of absolute encoder module, please refer to factory.

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Absolute Maximum Ratings 1, 2

Parameter

DC Supply VoltageInput VoltageOutput Voltage

Moisture Level (Non-Condensing)Operating TemperatureStorage Temperature

Symbol

VDVinVout%RHTATS

Limits

-0.3 to + 6.0-0.3 to +VD +0.3-0.5 to +VD +0.385-25 to 85- 40 to 100

Units

VVV%°C°C

Notes:

1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

2. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended Operating Condition

Values

Parameter

DC Supply VoltageOperating TemperatureInput High LevelInput Low Level

Symbol

VDTAVIHVLH

Min.

+ 4.5- 250.7*VD0

Typ.

+ 5.025

Max.

+5.5+85VD0.3*VD

Units

V°CVV

Notes

1

Notes:1. Voltage ripple of supply voltage, Vripple, should be within 100mVpp or less for improved accuracy.

Electrical Characteristics

Electrical Characteristics over Recommended Operating Range, typical at TA=25 °C and VD = 5V

Values

Parameter

Total Operating CurrentDigital Input-Pull Down CurrentDigital Input-Pull Up CurrentDigital Ouput-H-LevelDigital Ouput-L-LevelSCL Clock FrequencyDuty Cycle SCL Clock

Accuracy within one revolution1, 2, 3

Symbol

ItotalIpdIpuVOHVOLfSCLTLH

ConditionMinTyp.

25

MaxUnits

mA

-2030

IOH = 2 mAIOL = - 2 mA

VD -0.5 V0

-5160VD0.516

mAmAVVMHz

TLH = H/(L+H) fSCL = 5MHzRPM =80

Vripple <50mVpp

0.4

±2 bit

0.6

Signal frequency of A0, A09fA0, fA09250kHz

Notes:

1. LSB accuracy will also depend on mechanical precision of the shaft, bearings, hub etc. As the AEAS-7500 is a detached encoder set as differ-ent from AEAS-7000 series, which are modular, where final testing, programming and assembly take place at the customer facility, final ac-curacies of the encoder cannot be guaranteed by Avago.

2. Accuracy would be influenced by installation control and the bearing and shaft type being used.3. Other test conditions to determine accuracy are briefly listed as follows: (a) At nominal radial, tangential and gap position

(b) On dual preloaded bearing with absolute assembly total runout of not exceeding 0.01 mm TIR (c) Both VDD & VDDA RC filters placed not more than 20mm from header pins

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Pin Description

No.

12345

Pin Name

NCKORRPROBE_ONPCLSTCAL

DescriptionFunction

Do not use

Notes

Digital-inputDigital-InputDigital InputPositive edgeDigital InputPositive edgeNegative edgeDigital-InputDigital InputDigital-InputDigital-InputPositive EdgeDigital OutputDigital OutputDigital OutputSupply Voltage

Ground for supply voltageAnalog output

Ground for supply voltageAnalog OutputAnalog outputSupply VoltageAnalog OutputDigital OutputAnalog Output

1 = Gray Code Correction ActiveDo not use Do not use

Do not use unnecessarily

CMOS, internal puCMOS, internal pdCMOS, internal puCMOS, internal pd

6710111󰀲1󰀳1󰀴1󰀵16171819󰀲0󰀲1󰀲󰀲

MSBINVDINNSLSCLDOUTDODPROBEVDDGNDA09PGNDA0PA09NVDDAA0NLERRLEDR

1 = Most Significant Bit, MSB, invertedShift Register Input. Use for cascading only.Shift-register Shift (=0) / Load(=1) ControlShift-register Clock

Shift-Register Data Out (MSB first)DO signalDO9 signal+󰀵V Supply Digital

GND for 󰀵V supply analog/digitalA09 positive(+True diff.)GND for 󰀵V supply analog/digitalA0 positive(+True diff.)A09 negative(-True diff.)+󰀵V Supply AnalogA0 negative (- True dif)IR-LED Current Limit Signal

To be connected by user to the base of a NPN tran-sistor with a series resistor as per Figure 󰀵

CMOS, internal pdCMOS, internal pdCMOS, internal puCMOS, internal puCMOSS, 2mACMOS, 2mACMOS, 󰀲mA

CMOS, analog out

CMOS, analog outCMOS, analog out

CMOS, analog outCMOS, 󰀲mACMOS, analog out

Notes:1. Internal pu/pd = internal pull-up (typ. 50uA)/ pull-down (typ. 10uA) CMOS-transistor-Rs

Figure 2. Pinout Configuration

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LED Module Dimensions

Notes:

1 3rd Angle Projection

2. Dimensions are in millimeters

3. LED Module spatial misalignment tolerance absolute limits are as follows: (Refer to Figure 1 for directional indication) (a) Radial limit from nominal : ± 0.4 mm (b) Tangential limit from nominal : ± 0.4 mm

(c) LED module placement height at Z direction : + 1 mm, - 0.5 mm (as long as no contact with codewheel) (d) Tilting at XZ plane along PDA or Center line (CL) : ± 1 degreeFigure 3. LED Module Dimensions

Figure 4. Timing Diagram

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Using the AEAS-7500

IMPORTANT NOTE: The RC-filter combination, especially on VDDA, is used to filter spikes and transients and is strongly recommended. It is advised that the tantalum caps be put as close to the VDD and VDDA pins as possible.

Operation

After powering up the unit using VD =+5V and con-necting GND to ground, trigger input pins NSL and SCL using the timing diagram (Figure 4). NSL is a control pin for the internal shift register. NSL=1 is load mode while NSL=0 is shift mode for the shift register. When NSL=0

It is recommended to ground the PROBE_ON pin during

and combined with clock pulses, the serial Gray code will

normal operation.

be shifted out to DOUT bit by bit per every clock pulse.

Leave PCL unconnected. A09N and A0N are the negative Valid data of DOUT should be sampled at the low point cosine and sine waves, the negative versions of A09P and of the clock pulses.A0P.

The 16 bit serial gray code can be tapped out from pin

D0 is used to check the D0 signal. D0 is the digitized signal DOUT, most significant bit (D11) first. The rate of the of A0. DPROBE is used to check D09, the digitized signal of 16bit Gray code serial transfer rate is dependent on the A09. Recommended to be used for testing purpose only.SCL clock frequency. The faster the clock, the faster the

transfer rate. The maximum clock rate the AEAS-7500 can

KORR is for Gray Code correction for 12 bits resolution

take is 16 MHz, which means the entire 16 bit Gray code

only.

can be serially transferred out in 1 us.

MSBINV is for user to change between counting up and

Whenever NSL is high (load mode), the DOUT will have the

counting down for a given rotating direction. MSB(D11)

logic of the MSB (D11). After NSL goes low, the number of

will always be sent out to DOUT first

bits being transferred out will depend on the number of

LEDR is an internal voltage monitor which is linked to the clock pulses given to SCL. The default is 16 clock pulses Monitor channel. It should be connected to the base of an for the 16 bit Gray code. NPN transistor via a series resistor to control the LED bright-ness per the photodiodes’ need. (Refer to Figure 5)LERR will be high when the light output perceived by the photo diode array is low, and the LED current is under overdrive mode. This is an indicator when light intensity is at a critical stage affecting the performance of the encoder. It is caused either by contamination of the codewheel or LED degradation.

Analog-Outputs A09PA09NVDD VDD0R to 󰀲RVD (+󰀵V)(C's optional) min 󰀲µ󰀲TantalVDGNDD09DOUTSCLNSLDINMSBINVD0 GNDVDDVDDAGNDDOUTSCLNSLDINMSBINVSTCALSTCALPCLPROBE_ONIR-LED BC8󰀴6B󰀴7Rmin 100µTantalPCLLEDRLERRPROBE_ONKORR Configuration and Probe Control KORRLERRFigure 5. Schematic for using AEAS-7500

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Ordering Information

AEAS-7500-1GSG0

Single-turn, -25 to +85oC, detached encoder set, 5V, se-rial, 16 bit

Note:

For alignment process, please refer to Avago Technologies’ website forapplication note or contact factory.

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.59-3095EN - March 29, 2006