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HCF40192BEY资料

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HCF40192B

PRESETTABLE UP/DOWN COUNTER(DUAL CLOCK WITH RESET) BCD TYPE

s

s

s

s

s

sss

ss

INDIVIDUAL CLOCK LINES FOR COUNTING UP OR COUNTING DOWN

SYNCHRONOUS HIGH-SPEED CARRY AND BORROW PROPAGATION DELAYS FOR CASCADING

ASYNCHRONOUS RESET AND PRESET CAPABILITY

MEDIUM-SPEED OPERATION - fCL = 8MHz (typ.) AT 10 V

STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS

QUIESCENT CURRENT SPECIF. UP TO 20V5V, 10V AND 15V PARAMETRIC RATINGSINPUT LEAKAGE CURRENT

II = 100nA (MAX) AT VDD = 18V TA = 25°C100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B \"STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES\"

DIPSOPORDER CODES

PACKAGEDIPSOP

TUBEHCF40192BEYHCF40192BM1

T & R

HCF40192M013TR

DESCRIPTION

HCF40192B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP and SOP packages. HCF40192B Presettable BCD Up/Down Counterconsists of 4 synchronously clocked, GATED \"D\"type flip-flops connected as a counter. The inputsconsist of four individual jam lines, a PRESETENABLE control, individual CLOCK UP andCLOCK DOWN signals and a master RESET.Four buffered Q signal outputs, as well as CARRYPIN CONNECTIONand BORROW outputs for multiple-stage countingschemes, are provided. The counter is cleared sothat all outputs are in a low state by a high on theRESET line. A RESET is accomplishedasynchronously with the clock. Each output isindividually programmable asynchronously withthe clock to the level on the corresponding jaminput when the PRESET ENABLE control is low.The counter counts up one count on the positiveclock edge of the CLOCK UP signal, provided theCLOCK DOWN line is high. The counter countsdown one count on the positive clock edge of theCLOCK DOWN signal provided the CLOCK UPline is high. The CARRY and BORROW signalsare high when the counter is counts up or down.The CARRY signal goes low one-half clock cycleafter the counter reaches its maximum count inthe count-up mode. The BORROW signal goes

September 20021/12

元器件交易网www.cecb2b.com

HCF40192B

low one-half clock cycle after the counter reachesits minimum count in the count-down mode. Thecascading of multiple packages is easilyaccomplished without the need for additional

external circuitry by tying the BORROW andCARRY outputs to the CLOCK DOWN andCLOCK UP inputs, respectively, of the followingpackage.

IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No3, 2, 6, 7

451112131415, 1, 10, 9

816

SYMBOL

NAME AND FUNCTION

Q1 to Q4Flip-Flop OutputsCLOCK

Clock Down Input

DOWN

CLOCK UPClock Up InputPRESET

Preset Enable Input

ENABLECARRYCount Up (Carry)

BORROWCount Down (Borrow)RESET Reset InputJ1 to J4Data InputVSSNegative Supply Voltage

VDD

Positive Supply Voltage

FUNCTIONAL DIAGRAM

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HCF40192B

LOGIC DIAGRAM

TRUTH TABLE

CLOCK UPCLOCK DOWNHHHHXX(X) : Don’t Care

PRESET ENABLEHHHHRESETLLLLLHACTIONCOUNT UP NO COUNTCOUNT DOWNNO COUNTPRESETRESETXXLX3/12

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HCF40192B

TIMING DIAGRAM

INTERNAL LOGIC FLIP-FLOP

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HCF40192B

ABSOLUTE MAXIMUM RATINGS

SymbolVDDVIIIPDTopTstg

Supply VoltageDC Input VoltageDC Input Current

Power Dissipation per Package

Power Dissipation per Output TransistorOperating TemperatureStorage Temperature

Parameter

Value-0.5 to +22-0.5 to VDD + 0.5

± 10200100-55 to +125-65 to +150

UnitVVmAmWmW°C°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

SymbolVDDVITop

Supply VoltageInput Voltage

Operating Temperature

Parameter

Value3 to 200 to VDD-55 to 125

UnitVV°C

5/12

元器件交易网www.cecb2b.com

HCF40192B

DC SPECIFICATIONS

Test Condition

Symbol

Parameter

VI(V)0/50/100/150/200/50/100/155/010/015/0

0.5/4.51/91.5/13.54.5/0.59/113.5/1.52.54.69.513.50.40.51.5VO(V)

|IO|VDD(µA)(V)

5101520510155101551015510155510155101518

TA = 25°CMin.

Typ.0.040.040.040.08

4.959.9514.95

0.050.050.053.5711

1.534

-1.36-0.44-1.1-3.00.441.13.0

-3.2-1-2.6-6.812.66.8±10-55

-1.1-0.36-0.9-2.40.360.92.43.5711

1.534

-1.1-0.36-0.9-2.40.360.92.4

Max.51020100

4.959.9514.95

0.050.050.05

3.5711

1.534

Value-40 to 85°CMin.

Max.1503006003000

4.959.9514.95

0.050.050.05

-55 to 125°CMin.

Max.1503006003000

Unit

IL

Quiescent Current

µA

VOH

High Level Output Voltage

Low Level Output Voltage

High Level Input VoltageLow Level Input VoltageOutput Drive Current

VOL

VIH

VIL

IOH

IOL

Output Sink Current

Input Leakage Current

Input Capacitance

0/50/50/100/150/50/100/150/18

<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1

V

V

V

V

mA

mA

II

Any InputAny Input

±0.17.5

±1±1µApF

CI

The Noise Margin for both \"1\" and \"0\" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

6/12

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HCF40192B

DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)

Test Condition

Symbol

Parameter

VDD (V)5101551015510155101551015510155101551015510155101551015

Min.

Value (*)Typ.2501209020010070160806030015011010050404020152401501301208570904530

Max.50024018040020014032016012060030022020010080

nsUnit

tPLH tPHLPropagation Delay Time

Clock Up or Clock Down to Q Reset to Q

PE to Q

ns

Clock Up to Carry Clock Down to Borrow Reset or PR to Borrow or Carry

tTHL tTLHTransition Time

ns

ns

ns

trem*

Removal Time Reset or PE

tW

Clock Input Pulse Width ResetPE

804030480300260

ns

ns

240170140180906015155

ns

Clock

ns

tr tf

Clock Input Rise or Fall Time

Maximum Clock Input Frequency

µs

fCL

255.54811

MHz

(*) The time required for Reset or Preset Enable control to be removed before clocking (see timing diagram).

7/12

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HCF40192B

TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)RL = 200KΩ

RT = ZOUT of pulse generator (typically 50Ω)

WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)

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HCF40192B

WAVEFORM 2 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle)

TYPICAL APPLICATION: CASCADED COUNTER PACKAGES

9/12

元器件交易网www.cecb2b.com

HCF40192BPlastic DIP-16 (0.25) MECHANICAL DATAmm.DIM.MIN.a1Bbb1DEee3FILZ3.31.278.52.5417.787.15.10.1300.0500.510.770.50.25200.3350.1000.7000.2800.2011.65TYPMAX.MIN.0.0200.0300.0200.0100.7870.065TYP.MAX.inchP001C10/12元器件交易网www.cecb2b.com

HCF40192BSO-16 MECHANICAL DATADIM.Aa1a2bb1Cc1DEee3FGLMS3.84.60.59.85.81.278.4.05.31.270.628˚ (max.)0.1490.1810.019106.20.350.190.545˚ (typ.)0.3850.2280.0500.3500.1570.2080.0500.0240.3930.2440.1mm.MIN.TYPMAX.1.750.21.650.460.250.0130.0070.0190.003MIN.inchTYP.MAX.0.0680.0070.00.0180.010PO13H11/12元器件交易网www.cecb2b.com

HCF40192B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.

© The ST logo is a registered trademark of STMicroelectronics© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved

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