ALU and Barrel Shifter
DS3705ISSUE 3.0November 1998
The PDSP1601 is a high performance 16-bit arithmeticlogic unit with an independent on-chip 16-bit barrel shifter.The PDSP1601A has two operating modes giving 20MHz or10MHz register-to-register transfer rates.
The PDSP1601 supports Multicycle multiprecisionoperation. This allows a single device to operate at 20MHz for16-bit fields, 10MHz for 32-bit fields and 5MHz for -bit fields.The PDSP1601 can also be cascaded to produce wider wordsat the 20MHz rate using the Carry Out and Carry In pins. TheBarrel Shifter is also capable of extension, for example thePDSP1601 can used to select a 16-bit field from a 32-bit inputin 100ns.
PIN 1A INDEX MARKON TOP SURFACEABCDEFGHJKL1110987654321AC84FEATURES
sssssssss
16-bit, 32 instruction 20MHz ALU
16-bit, 20MHz Logical, Arithmetic or Barrel ShifterIndependent ALU and Shifter Operation4 x 16-bit On Chip Scratchpad RegistersMultiprecision Operation; e.g. 200ns -bitAccumulate
Three Port Structure with Three Internal FeedbackPaths Eliminates I/O BottlenecksBlock Floating Point Support
300mW Maximum Power Dissipation
84-pin Pin Grid Array or 84 Contact LCC Packagesor 100 pin Ceramic Quad Flat Pack
GC100https://www.ichunt.comFig.1 Pin connections - bottom viewAPPLICATIONSORDERING INFORMATION
PDSP1601 MC GGCRPDSP1601A BO ACN.B
10MHz MIL883 Screened -QFP package
20MHz Industrial - PGApackage
sssss
Digital Signal ProcessingArray ProcessingGraphics
Database Addressing
High Speed Arithmetic Processors
ASSOCIATED PRODUCTS
PDSP16112PDSP16116PDSP16318PDSP16330
Complex Multiplier
16 x 16 Complex MultiplierComplex AccumulatorPythagoras Processor
Further details of the Military grade part areavailable in a separate datasheet (DS3763)
1
PDSP1601/PDSP1601A
PIN DESCRIPTION
AC pinFunctionAC pinFunctionAC pinFunctionAC pinFunctionC6A6A5B5C5A4B4A3A2B3A1B2C2B1C1D2D1E3E2E1F1
IA4MSBMSSB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0CEBCLK
F3G3G1G2F1H1H2J1K1J2L1K2K3L2L3K4L4J5K5L5K6
GNDMSA0MSA1A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0CEAMSC
J6J7L7K7L6L8K8L9L10K9L11K10J10K11J11H10H11F10G10G11G9
IS0IS1IS2IS3SV0SV1SV2SV3SVOERS0RS1VCCRS2C0C1C2C3C4C5C6C7
F9F11E11E10E9D11D10C11B11C10A11B10B9A10A9B8A8B6B7A7C7
GNDC8C9C10C11C12C13C14C15OEBFPVCCCORA0RA1RA2CIIA0IA1IA2IA3
GC123456710111213141516171819202122232425
SIGN/CN/CN/CN/CVCCC0RA0RA1RA2CIIA0IA1IA2IA3IA4MSBMSSB15B14B13B12B11B10B9B8
GCSIGGCSIGGC767778798081828384858687809192939495969799100
SIGN/CN/CN/CN/CVCCRS2C0C1C2C3C4C5C6C7GNDC8C9C10C11C12C13C14C15OEBFP
2651N/CN/C
https://www.ichunt.com2752N/CN/C
28
293031323334353637383940414243444547484950
N/CN/CB7B6B5B4B3B2B1B0CEBCLKGNDMSA0MSA1A15A14A13A12A11A10A9A8
53545556575859606162636566676869707172737475
N/CN/CA7A6A5A4A3A2A1A0CEAMSCIS0IS1IS2IS3SV0SV1SV2SV3SVOERS0RS1
N/C = not connected - leave open circuitAll GND and VDD pin must be used
2
PDSP1601/PDSP1601A
PIN DESCRIPTIONS
SymbolMSBMSSB15 - B0CEBCLK
MSA0 - MSA1A15 - A0CEAMSCIS0 - IS3SV0 - SV3
Description
ALU B-input multiplexer select control.1 This input is latched internally on the rising edgeof CLK.
Shifter Input multiplexer select control.1 This input is latched internally on the rising edgeof CLK.
B Port data input. Data presented to this port is latched into the input register on the risingedge of CLK. B15 is the MSB.
Clock enable, B Port input register. When low the clock to this register is enabled.Common clock to all internal registered elements. All registers are loaded, and outputschange on the rising edge of CLK.
ALU A-input multiplexer select control.1 These inputs are latched internally on the risingedge of CLK.
A Port data input. Data presented to this port is latched into the input register on the risingedge of CLK. A15 is the MSB.
Clock enable, A Port input register. When low the clock to this register is enabled.C-Port multiplexer select control.1 This input is latched internally on the rising edgeof CLK.
Instruction inputs to Barrel Shifter, IS3 = MSB.1 These inputs are latched internally on therising edge of CLK.
Shift Value I/O Port. This port is used as an input when shift values are supplied from
external sources, and as an output when Normalise operations are invoked. The I/O functionsare determined by the IS0 - IS3 instruction inputs, and by the SVOE control.The shift value is latched internally on the rising edge of CLK.
SV Output enable. When high the SV port can only operate as an input. When low the SVport can act as an input or as an output, according to the IS0 - IS3 instruction. This pin shouldbe tied hihg or low, depending upon the application.
Instruction inputs to Barrel Shifter registers.1 These inputs are latched internally on therising edge of CLK.
C Port data output. Data output on this port is selected by the C output multiplexer.C15 is the MSB.
Output enable. The C Port outputs are in high impedance condition when this control is high.Block Floating Point Flag from ALU, active high.Carry out from MSB of ALU.
Instruction inputs to ALU registers.1 These inputs are latched internally on the risingedge of CLK.
Carry in to LSB of ALU.
Instruction inputs to ALU.1 IA4 = MSB. These inputs are latched internally on the risingedge of CLK.
+5V supply: Both Vcc pins must be connected.0V supply: Both GND pins must be connected.
SVOEhttps://www.ichunt.comRS0, RS1RS2C0 - C15OEBFPCORA0 - RA2CIIA0 - IA3IA4VccGNDNOTES
1. All instructions are executed in the cycle commencing with the rising edge of the CLK which latches the inputs.
3
PDSP1601/PDSP1601A
A INPUT16A REGCEAB INPUT16B REGCEBA MUXMSA0-12B MUXMSBS MUXMSSBFPCOAALUBIA0-4CI5BARREL SHIFTERSHIFTCONTROLIS0-3SV0-3SVOERAD-233RS0-2ALU REG FILELEFT REG.RIGHT REG.SHIFTER REG FILELEFT REG.RIGHT REG.C MUXMSCOE16COUTFig.2 PDSP1601 block diagramFUNCTIONAL DESCRIPTION
The PDSP1601 contains four main blocks: the ALU, theBarrel Shifter and the two Register Files.The ALU
active the ALU result must have overflowed into the 16th (sign)bit, (this flag is only valid whilst the most significant 16 bit byteis being processed). The zero condition is active if the resultfrom the ALU is equal to zero. For multiprecision operationsthe zero flag must be active for all of the 16 bit bytes of anextended word.
The BFP flag is programmed by executing on of the fourSBFXX instructions (see Table 1). During the execution of anyof these four instructions, the output of the ALU is forced tozero.
Multicycle/Cascade Operation
The ALU arithmetic instructions contain two or threeoptions for each arithemtic operation.
The ALU is designed to operate with two's complementarithmetic, requiring a one to be added to the LSB for allsubtract operations. The instructions set includes instructionsthat will force a one into the LSB, e.g. MIAX1, AMBX1, BMAX1(see Table 1).
These instructions are used for the least significant 16 bitbyte of any subtract operation.
The user has an option of cascading multiple devices, ormulticycling a single device to extend the arithmetic precision.Should the user cascade multiple devices, then the cascadearithmetic instructions using the external CI input should beemployed for all but the least significant 16 bit byte, e.g. MIACI,APBCI, BMACI (see Table 1).
Should the user multicycle a single device, then theMulticycle Arithmetic instructions, using the internallyregistered CO bit should be employed for all but the leastsignificant 16 bit byte, e.g. MIACO, APBCO, AMBCO,BMACO (see Table 1).
https://www.ichunt.comThe ALU supports 32 instructions as detailed in Table 1.The inputs to the ALU are selected by the A and B MUXs.Data will fall through from the selected register through the Aor B input MUXs and the ALU to the ALU output register file in50ns for the PDSP1601A (100ns for the PDSP1601).
The ALU instructions are latched, such that the instructionwill not start executing until the rising edge of CLK latches theinstruction into the device.
The ALU accepts a carry in from the CI input and suppliesa carry out to the CO output. Additionally, at the end of eachcycle, the carry out from the ALU is loaded into an internal 1bit register, so that it is available as an input to the ALU on thenext cycle. In the manner, multicycle, multiprecisionoperations are supported. (See MULTICYCLE CASCADEOPERATIONS).BFP Flag
The ALU has a user programmable BFP flag. This flagmay be programmed to become active at any one of fourconditions. Two of these conditions are intended to supportBlock Floating Point operations, in that they provide flagsindicating that the ALU result is within a factor of two or four ofoverflowing the 16 bit number range. For multiprecisionoperations the flag is only valid whilst the most significant 16bit byte is being processed. In this manner the BFP flag maybe used over any extended word width.
The remaining two conditions detect either an overflowcondition or a zero result. For the overflow condition to be
4
PDSP1601/PDSP1601A
Table 1 ALU instructions1a. ARITHMETIC INSTRUCTIONS
Inst000102030405060708090A0B0C0D0E0F
IA4-AI0Mnemonic00000000010001000011001000010100110001110100001001010100101101100011010111001111
CLRXXMIAX1MIACIMIACOA2SGNA2RALA2RARA2RSXAPBCIAPBCOAMBX1AMBCIAMBCOBMAX1BMACIBMACO
OperationRESETMINUS AMINUS AMINUS AA/2A/2A/2A/2
A PLUS BA PLUS BA MINUS BA MINUS BA MINUS BB MINUS AB MINUS AB MINUS A
Function
CLEAR ALL REGISTERSNA Plus 1NA Plus CINA Plus COA/2 Sign ExtendA/2 with RAL LSBA/2 with RAR LSBA/2 with RSX LSBA Plus B Plus CIA Plus B Plus COA Plus NB Plus 1A Plus NB Plus CIA Plus NB Plus CONA Plus B Plus 1NA Plus B Plus CINA Plus B Plus CO
Mode---------LSBYTECASCADEMULTICYCLEMSBYTEMULTICYCLEMULTICYCLEMULTICYCLECASCADEMULTICYCLELSBYTECASCADEMULTICYCLELSBYTECASCADEMULTICYCLE
1b. LOGICAL INSTRUCTIONS
Inst1011121314151617
IA4-AI0Mnemonic1000010001100101001110100101011011010111
ANXABANANBANNABORXABORNABXORABPASXAPASNA
OperationA AND BA AND NBNA AND BA OR BNA OR BA XOR BPASS AINVERT A
FunctionA. BA. NBNA. BA + BNA + BA XOR BANA
https://www.ichunt.com1c. CONTROL INSTRUCTIONS
Inst18191A1B1C1D1E1F
IA4-AI0Mnemonic1100011001110101101111100111011111011111
SBFOVSBFU1SBFU2SBFZEOPONEOPBYTOPNIBOPALT
Operation
Set BFP Flag to OVR, Force ALU output to zeroSet BFP Flag to UND 1 Force ALU output to zeroSet BFP Flag to UND 2 Force ALU output to zeroSet BFP Flag to ZERO Force ALU output to zeroOutput 0001 HexOutput 00FF HexOutput 000F HexOutput 5555 Hex
KEYABCICORALRARRSX
MNEMONICS
= A input to ALU= B input to ALU
= External Carry in to ALU
= Internally Registered Carry out from ALU= ALU Register (Left)= ALU Register (Right)
= Shifter Register (Left or Right)
CLRXXMIAXXA2XXXAPBXXAMBXXBMAXXANX-YORX-YXORXYPASXXSBFXXOPXXX
Clear All Registers to zeroMinus A,XX= Carry in to LSBA Divided by 2,XXX= Source of MSBA Plus B,XX= Carry in to LSBA Minus B,XX= Carry in to LSBB Minus A,XX= Carry in to LSBANDX= Operand 1, Y = Operand 2ORX= Operand 1, Y = Operand 2Exclusive ORX= Operand 1, Y = Operand 2PassXX= OperandSet BFP FlagXX= FunctionOutput ConstantXXX
5
PDSP1601/PDSP1601A
Divide by Two
The ALU has four (A2SGN, A2RAL, A2RAR, A2RSX)instructions used for right shifting (dividing by two) extendedprecision words. These words, (up to bits) may be storedin the two on-chip register files. When the least significant 16bit word is shifted, the vacant MSB must be filled with the LSBfrom the next most significant 16 bit byte. This is achieved viathe A2RAL, A2RAR or A2RSX instructions which indicate thesource of the new MSB (see ALU INSTRUCTION SET).
When the most significant 16 bit byte is right shifted, theMSB must be filled with a duplicate of the original MSB so asto maintain the correct sign (Sign Extension). This operationis achieved via the A2SGN instruction (see Table 1).Constants
The ALU has four instructions (OPONE, OPBYT, OPNIB,OPALT) that force a constant value onto the ALU output.These values are primarily intended to be used as masks, orthe seeds for mask generation, for example, the OPONEinstruction will set a single bit in the least significant position.This bit may be rotated any where in the 16 bit field by theBarrel Shifter, allowing the AND function of the ALU to performbit-pick operations on input data.CLR
The ALU instruction CLRXX is used as a Master Reset forthe entire device. This instruction has the effect of:1.2.3.4.5.
Clearing ALU and Barrel Shifter register files to zero.Clearing A and B port input registers to zero.
Clearing the R1 and R2 shift control registers to zero.Clearing the internally registered CO bit to zero.
Programming the BFP flag to detect overflow conditions.
Inst01234567ABCDEF
IS3-IS0Mnemonic0000000100100011010001010110011110001001101010111100110111101111
LSRSVLSLSVBSRSVBSLSVLSRR1LSLR1LSRR2LSLR2LR1SVLR2SVASRSVASRR1ASRR2NRMXXNRMR1NRMR2
The Barrel Shifter
The Barrel Shifter supports 16 instructions as detailed inTable 2. The input to the Barrel Shifter is selected by the SMUX. Data will fall through from the selected register, throughthe S MUX and the Barrel Shifter to the shifter output registerfile in 50ns for the PDSP1601A (100ns for the PDSP1601).
The Barrel Shifter instructions are latched, such that theinstructions will not start executing until the rising edge of CLKlatches the instruction into the device.
The Barrel Shifter is capable of Logical Arithmetic or BarrelShifts in either direction.A.B.C.
Logical shifts discard bits that exit the 16 bit field and fillspaces with zeros.
Arithmetic shifts discard bits that exit the 16 bit field andfill spaces with duplicates of the original MSB.
Barrel Shifts rotate the 16 bit fields such that bits tha exitthe 16 bit field to the left or right reappear in the vacantspaces on the right or left.
The amount of shift applied is encoded onto the 4 bit BarrelShifter input as illustrated in Table 3. The type of shift and theamount are determined by the shift control block. The shiftcontrol block (see Fig.3) accepts and decodes the four bit ISO-3 instruction. The shift control block contains a priorityencoder and two user programmable 4 bit registers R1 andR2.
There are four possible sources of shift value that can bepassed onto the Barrel Shifter, there are:1.2.3.4.
The Priority EncoderThe SV inputThe R1 registerThe R2 registerOperation
https://www.ichunt.comI/OIIIIXXXXIIIXXOOO
Logical Shift Right by SVLogical Shift Left by SVBarrel Shift Right by SVBarrel Shift Left by SVLogical Shift Right by R1Logical Shift Left by R1Logical Shift Right by R2Logical Shift Left by R2Load Register 1 From SVLoad Register 2 From SVArithmetic Shift Right by SVArithmetic Shift Right by R1Arithmetic Shift Right by R2Normalise Output PE
Normalise Output PE, Load R1Normalise Output PE, Load R2
Table 2 Barrel shifter instructionsKEYSVR1R2PEIOX
MNEMONICS
= Shift Value= Register 1= Register 2
= Priority Encoder Output
=> SV Port operates as an Input=> SV Port operates as an Output=> SV Port in a High Impedance State
LSXYYBSXYYASXYYLXXYYNRMYY
Logical Shift,X= Direction YY = Source of Shift ValueBarrel Shift,X= Direction YY = Source of Shift ValueArithmetic Shift,X= Direction YY = Source of Shift ValueLoadXX= Target YY = Source
Normalise by PE, Output PE value on SV Port, Load YY Reg
6
PDSP1601/PDSP1601A
SV30000000011111111
SV20000111100001111
SV10011001100110011
SV00101010101010101
ShiftNo shift1 place2 places3 places4 places5 places6 places7 places8 places9 places10 places11 places12 places13 places14 places15 places
(1)Priority encode the 16 bit input to the Barrel Shifter andplace the 4 bit value in either of the R1 or R2 registers andoutput the value on the SV port (if enabled by SVOE).(2)Shift the 16 bit input by the amount indicated by thePriority Encoder such that the output from the Barrel Shifter isa normalised value.SV Input
If the SV port is selected as the source of the shift value,then the input to the Barrel Shifter is shifted by the value storedin the internal SV register.
SVOEThe SV port acts as an input or an output depending uponthe IS0-3 instruction. If the user does not wish to use thenormalise instructions, then the SV port mat be forced to beinput only by typing SVOE control high. In this mode the SVport may be considered an extension of the instruction inputs.R1 and R2 Registers
The R1 and R2 registers may be loaded from the PriorityEncoder (NRMR1 and NRMR2) or from the SV input (LR1SV,LR2SV).
Whilst the latter two instructions are executing, the BarrelShifter will pass its input to the output unshifted.
Table 3 Barrel shifter codesPriority Encoder
If the priority encoder is selected as the source of the shiftvalue (instructions:- NRMXX, NRMR1, MRMRZ), then withinone 100ns cycle or two 50ns cycles for the PDSP1601A (one200ns or two 100ns cycles for the PDSP1601), the shiftcircuitry will:
https://www.ichunt.com16INSTRUCTIONDECODEPRIORITY ENCODER4IS0-34MUX4SVMUXMUXSVOER1R2Fig.3 Shift control block7
PDSP1601/PDSP1601A
The Register Files
There are two on-chip register files (ALU and Shifter), eachcontaining two 16 bit registers and each supporting 8instructions (see Table 4). The instructions for the ALUregister file and the Barrel Shifter Register file are the same.
The Inputs to the register files come from either the ALU orthe Barrel Shifter, and are loaded into the Register files on therising edge of CLK.
The register file instructions are latched such that theinstruction will not start executing until the rising edge of the
CLK latches the instruction into the device.
The register file instructions (see Table 4) allow input datato be loaded into either, neither or both of the registers. Datais loaded at the end of the cycle in which the instruction isexecuting.
The register file instructions allow the output to be sourcedfrom either of the two registers, the selected output will be validduring the cycle in which the instruction is executing.
8
ALU REGISTER INSTRUCTIONS
InstRA2-RA0MnemonicOperation
0000LLRRRLoad Left Reg Output Right Reg1001LRRLRLoad Right Reg Output Left Reg2010LLRLRLoad Left Register, Output Left Reg3011LRRRRLoad Right Register, Output Right Reg4100LBRLRLoad Both Registers, Output Left Reg5101NOPRRNo Load Operation, Output Right Reg6110NOPLRNo Load Operation, Output Left Reg7
111
NOPPS
No Load Operation, Pass ALU Result
SHIFTER REGISTER INSTRUCTIONS
InstRA2-RA0MnemonicOperation
000012https://www.ichunt.comLLRRRLoad Left Reg Output Right Reg001LRRLRLoad Right Reg Output Left Reg010LLRLRLoad Left Register, Output Left Reg3011LRRRRLoad Right Register, Output Right Reg4100LBRLRLoad Both Registers, Output Left Reg5101NOPRRNo Load Operation, Output Right Reg6110NOPLRNo Load Operation, Output Left Reg
7
111
NOPPS
No Load Operation, Pass Barrel Shifter Result
Table 4 ALU and shift register instructions mnemonicsMNEMONICS
LXXYYLoad XX = Target,YY= Source of OutputLBOXXLoad Both Registers,XX= Source of OutputNOPXXNo Load Operation,XX
= Source of Output
PDSP1601/PDSP1601A
Multiplexers
There are four user selectable on-chip multiplexers (A-MUX, B-MUX, S-MUX and C-MUX).
The MUX instructions are latched such that the instructionwill not start executing until the rising edge of CLK latches theThese four multiplexers support instructions as tabulatedinstruction onto the device.
in Table 5.
MSA1
MSA0Output
A-MUX
MARAX00ALU REGISTER FILE OUPUTMAAPR01A-PORT INPUTMABPR10B-PORT INPUT
MARSX
11
SHIFTER REGISTER FILE OUTPUT
MSB
Output
B-MUX
0B-PORT INPUT
1SHIFTER REGISTER FILE OUTPUT
MSS
Output
S-MUX
0B-PORT INPUT
1SHIFTER REGISTER FILE OUTPUT
MSC
Output
C-MUX
0ALU REGISTER FILE OUTPUT
1
SHIFTER REGISTER FILE OUTPUT
https://www.ichunt.comTable 59
PDSP1601/PDSP1601A
INSTRUCTION SET
ALU Arithmetic InstructionsMnemonicCLRXX
Op Code<00>
Function
On the rising edge of CLK at the end of the cycle in which this instruction is executing, theA Port, B Port, ALU, Barrel Shifter, and Shift Control Registers will be loaded with zeros.The internal registered CO will also be set to zero, and the BFP flag will be set to activateon overflow conditions.
The A input to the ALU is inverted and a one is added to the LSB.The A input to the ALU is inverted and the CI input is added to the LSB.
The A input to the ALU is inverted and the CO output from the ALU on the previous cycleis added to the LSB.
The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacantMSB is filled by duplicating the original MSB (Sign Extension).
The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacantMSB is filled with the LSB from the ALU register.
The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacantMSB is filled with the LSB from the ALU register.
The A input to the ALU is right shifted one bit position. The LSB is discarded, and the vacantMSB is filled with the LSB from the B input to the ALU.
The A input to the ALU is added to the B input, and the CI input is added to the LSB.The A input to the ALU is added to the B input, and the CO out from the ALU on the previouscycle is added to the LSB.
The A input to the ALU is added to the inverted B input, and a one is added to the LSB.The A input to the ALU is added to the inverted B input, and the CI input is added to theLSB.
The A input to the ALU is added to the inverted B input, and the CO out from the ALU onthe previous cycle is added to the LSB.
The inverted A input to the ALU is added to the B input, and a one is added to the LSB.The inverted A input to the ALU is added to the B input, and the CI input is added to theLSB.
The inverted A input to the ALU is added to the B input, and the CO out from the ALU onthe previous cycle is added to the LSB.
MIAX1MIAC1MIACOA2SGNA2RALA2RARA2RSXAPBCIAPBCOAMBX1AMBCIAMBCOBMAX1BMAC1BMACO
<01><02><03><04><05><06><07><08><09><0A><0B><0C><0D><0E><0F>
https://www.ichunt.comALU Logical InstructionsMnemonicANXABANANBANNABORXABORNABXORABPASXAPASNA
Op Code<10><11><12><13><14><15><16><17>
Function
The A input to the ALU is logically 'ANDed' with the B input.
The A input to the ALU is logically 'ANDed' with the inverse of the B input.The inverse of the A input to the ALU is logically 'ANDed' with the B input.The A input to the ALU is logically 'ORed' with the B input.The inverse A input to the ALU is logically 'ORed' with the B input.The A input to the ALU is logically Exclusive-ORed with the B input.The A input to the ALU is passed to the output.
The inverse of the A input to the ALU is passed to the output.
10
PDSP1601/PDSP1601A
ALU Control InstructionsMnemonicSBFOV
Op Code<18>
Function
The BFP flag is programmed to activate when an ALU operation causes an overflow of the16 bit number range. This flag is logically the exclusive-or of the carry into and out of theMSB of the ALU. For the most significant Byte this flag indicates that the result of anarithmetic two's complement operation has overflowed into the sign bit. The output of theALU is forced to zero for the duration of this instruction.
The BFP flag is programmed to activate when an ALU operation comes within a factor oftwo of causing an overflow of the 16 bit number range. For the most significant Byte thisflag indicates that the result of an arithmetic two's complement operation is within a factorof two of overflowing into the sign bit. The output of the ALU is forced to zero for the durationof this instruction.
The BFP flag is programmed to activate when an ALU operation comes within a factor offour of causing an overflow of the 16 bit number range. For the most significant Byte thisflag indicates that the result of an arithmetic two's complement operation is within a factorof four of overflowing into the sign bit. The output of the ALU is forced to zero for the durationof this instruction.
The BFP flag is programmed to activate when an ALU operation causes a result of zero.The output of the ALU is forced to zero for the duration of this instruction. During theexecution of this instruction the BFP flag will become active.
The ALU will output the binary value 0000000000000001, the MSB on the left.The ALU will output the binary value 0000000011111111, the MSB on the left.The ALU will output the binary value 0000000000001111, the MSB on the left.The ALU will output the binary value 0101010101010101, the MSB on the left.
SBFU1
<19>
SBFU2
<1A>
SBFZE
<1B>
OPONEOPBYTOPNIBOPALT
<1C><1D><1E><1F>
Barrel Shifter InstructionsMnemonicLSRSV
Op Code<0>
https://www.ichunt.comFunction
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated bythe magnitude of the four bit number present in the SV register. The LSBs are dicarded,and the vacant MSBs are filled with zeros.
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by themagnitude of the four bit number present in the SV register. The LSBs are dicarded, andthe vacant MSBs are filled with zeros.
The 16 bit input to the Barrel Shifter is rotated to the right by the number of places indicatedby the magnitude of the four bit number present in the SV register. The LSBs that exit the16 bit field to the right, reappear in the vacant MSBs on the left.
The 16 bit input to the Barrel Shifter is rotated to the left by the number of places indicatedby the magnitude of the four bit number present in the SV register. The LSBs that exit the16 bit field to the right, reappear in the vacant MSBs on the right.
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated bythe magnitude of the four bit number resident within the R1 register. The LSBs arediscarded, and the vacant MSBs are filled with zeros.
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by themagnitude of the four bit number resident within the R1 register. The LSBs are discarded,and the vacant LSBs are filled with zeros.
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated bythe magnitude of the four bit number resident within the R2 register. The LSBs arediscarded, and the vacant MSBs are filled with zeros.
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by themagnitude of the four bit number resident within the R2 register. The LSBs are discarded,and the vacant LSBs are filled with zeros.
LSLSV
<1>
BSRSV
<2>
BSLSV
<3>
LSRR1
<4>
LSLR1
<5>
LSRR2
<6>
LSLR2
<7>
11
PDSP1601/PDSP1601A
MnemonicLR1SV
Op Code<8>
Function
On the rising edge of CLK at the end of the cycle in which this instruction is executing, theR1 register will be loaded with the data present on the SV port. The input to the BarrelShifter will be passed onto the output unshifted.
On the rising edge of CLK at the end of the cycle in which this instruction is executing, theR2 register will be loaded with the data present on the SV port. The input to the BarrelShifter will be passed onto the output unshifted.
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated bythe magnitude of the four bit number present in the SV register. The LSBs are discarded,and the vacant MSBs are filled with duplicates of the original MSB. (Sign Extension).The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated bythe magnitude of the four bit number resident within the R1 register. The LSBs arediscarded, and the vacant MSBs are filled with duplicates of the original MSB.(Sign Extension).
The 16 bit input to the Barrel Shifter is right shifted by the number of places indicated bythe magnitude of the four bit number resident within the R2 register. The LSBs arediscarded, and the vacant MSBs are filled with duplicates of the original MSB.(Sign Extension).
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by themagnitude of the four bit number output from the Priority Encoder. This value is also outputon the SV port (provided SVOE is low).The effect of this operation is to left shift the input by the necessary amount
(max 15 places) to result in the MSB and the next most significant bit being different. Thishas the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filledwith zeros.
The 16 bit input to the Barrel Shifter is left shifted by the number of places indicated by themagnitude of the four bit number output from the Priority Encoder. This value is also loadedinto the R1 register at the end of the cycle, and is output on the SV port (provided SVOEis low).
The effect of this operation is to left shift the input by the necessary amount
(max 15 places) to result in the MSB and the next most significant bit being different. Thishas the effect of eliminating unnecessary Sign Bits, and hence Normalising the input data.The MSBs shifted out to the left are discarded, and the vacant LSBs on the right are filledwith zeros.
LR2SV
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ASRSV
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